參數(shù)資料
型號: HYB18T512800AF-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 15/117頁
文件大?。?/td> 2102K
代理商: HYB18T512800AF-3S
Data Sheet
15
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
be precharged, the bank is selected by BA[1:0]. The
address inputs also provide the op-code during Mode
Register Set commands.
Control Signals
×
16 organization
K7
RAS
L7
CAS
K3
WE
L8
CS
Address Signals
×
4/
×
8 organizations
G2
BA0
G3
BA1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
I
I
SSTL
SSTL
Bank Address Bus 1:0
Note:BA[1:0] define to which bank an Activate, Read, Write or
Precharge command is being applied. BA[1:0] also
determines if the mode register or extended mode register
is to be accessed during a MRS or EMRS(1) cycle
Address Signal 12:0, Address Signal 10/Autoprecharge
Note:Address Signal 10/Autoprecharge provides the row address
for Activate commands and the column address and Auto-
Precharge bit A10 (=AP) for Read/Write commands to
select one location out of the memory array in the respective
bank. A10(=AP) is sampled during a Precharge command
to determine whether the Precharge applies to one bank
(A10=LOW) or all banks (A10=HIGH). If only one bank is to
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
K7
L2
L8
Address Signal 13
Note:512 Mbit components
Note:256 Mbit components
NC
Address Signals
×
16 organization
L2
BA0
L3
BA1
L1
NC
I
I
SSTL
SSTL
Bank Address Bus 1:0
Table 4
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Buffer
Type
Function
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