參數(shù)資料
型號(hào)： HYB18T512800AC-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù)： 63/96頁
文件大?。?/td> 2153K
代理商： HYB18T512800AC-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
63
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
2.11
Other Commands
2.11.1
The No Operation Command (NOP) should be used in
cases when the SDRAM is in a idle or a wait state. The
purpose of the No Operation Command is to prevent
the SDRAM from registering any unwanted commands
between operations. A No Operation Command is
No Operation Command
registered when CS is low with RAS, CAS, and WE
held high at the rising edge of the clock. A No Operation
Command will not terminate a previous operation that
is still executing, such as a burst read or write cycle.
2.11.2
The Deselect Command performs the same function as
a No Operation Command. Deselect Command occurs
Deselect Command
when CS is brought high, the RAS, CAS, and WE
signals become don’t care.
2.12
Input Clock Frequency Change
During operation the DRAM input clock frequency can
be changed under the following conditions:
During Self-Refresh operation
DRAM is in Precharge Power-down mode and ODT
is completely turned off.
The DDR2-SDRAM has to be in Precharged Power-
down mode and idle. ODT must be already turned off
and CKE must be at a logic “l(fā)ow” state. After a minimum
of two clock cycles after
t
RP
and
t
AOFD
have been
satisfied the input clock frequency can be changed. A
stable new clock frequency has to be provided, before
CKE can be changed to a “high” logic level again. After
t
XP
has been satisfied a DLL RESET command via
EMRS(1) has to be issued. During the following DLL re-
lock period of 200 clock cycles, ODT must remain off.
After the DLL-re-lock period the DRAM is ready to
operate with the new clock frequency.
Figure 61
Input Frequency Change Example during Precharge Power-Down mode
NOP
NOP
T0
T2
T1
T3
T4
Tx
Tx+1
Ty
CMD
NOP
NOP
NOP
NOP
NOP
DLL
RESET
Ty+2
Ty+3
CKE
Frequency Change
occurs here
NOP
NOP
Frequ.Ch.
Tz
tXP
Stable new clock
before power-down exit
CK, CK
tRP
tAOFD
Minimum 2 clocks
required before
changing the frequency
Ty+1
NOP
Valid
Command
200 clocks
ODT is off during
DLL RESET
相關(guān)PDF資料
PDF描述
HYB18T512800AC-5 M39012 MIL RF CONNECTOR
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HYB25D128160AT-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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