參數(shù)資料
型號(hào)： HYB18T512800AC-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： M39012 MIL RF CONNECTOR
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁(yè)數(shù)： 17/96頁(yè)
文件大?。?/td> 2153K
代理商： HYB18T512800AC-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Overview
Data Sheet
17
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
DM, LDM, UDM
Input
Input Data Mask:
DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM is
sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM and UDM are the input mask signals for
×
16
components and control the lower or upper bytes. For
×
8 components the data mask
function is disabled, when RDQS / RQDS are enabled by EMRS(1) command.
Bank Address Inputs:
BA[1:0] define to which bank an Activate, Read, Write or
Precharge command is being applied. BA[1:0] also determines if the mode register or
extended mode register is to be accessed during a MRS or EMRS(1) cycle.
Address Inputs:
Provides the row address for Activate commands and the column
address and Auto-Precharge bit A10 (=AP) for Read/Write commands to select one
location out of the memory array in the respective bank. A10 (=AP) is sampled during
a Precharge command to determine whether the Precharge applies to one bank
(A10=low) or all banks (A10=high). If only one bank is to be precharged, the bank is
selected by BA[1:0]. The address inputs also provide the op-code during Mode
Register Set commands.
Row address A13 is used on
×
4 and
×
8 components only.
Data Inputs/Output:
Bi-directional data bus. DQ[0:3] for
×
4 components, DQ[0:7] for
×
8 components, DQ[0:15] for
×
16 components.
Data Strobe:
output with read data, input with write data. Edge aligned with read data,
centered with write data. For the
×
16, LDQS corresponds to the data on LDQ[7:0];
UDQS corresponds to the data on UDQ[7:0]. The data strobes DQS, LDQS, UDQS
may be used in single ended mode or paired with the optional complementary signals
DQS, LDQS, UDQS to provide differential pair signaling to the system during both
reads and writes. An EMRS(1) control bit enables or disables the complementary data
strobe signals.
Read Data Strobe:
For the
×
8 components a RDQS, RDQS pair can be enabled via
the EMRS(1) for read timing. RDQS, RDQS is not supported on
×
4 and
×
16
components. RDQS, RDQS are edge-aligned with read data. If RDQS, RDQS is
enabled, the DM function is disabled on
×
8 components.
No Connect:
no internal electrical connection is present
DQ Power Supply:
1.8 V
±
0.1 V
DQ Ground
DLL Power Supply:
1.8 V
±
0.1 V
DLL Ground
Power Supply:
1.8 V
±
0.1 V
Ground
Reference Voltage
BA2, A[15:14] are additional address pins for future generation DRAMs and are not
connected on this component.
BA[1:0]
Input
A[13:0]
Input
DQx
Input/
Output
Input/
Output
DQS, (DQS)
LDQS, (LDQS),
UDQS,(UDQS)
RDQS, (RDQS)
Input/
Output
NC
V
DDQ
V
SSQ
V
DDL
V
SSDL
V
DD
V
SS
V
REF
(BA2), A[15:14]
—
Supply
Supply
Supply
Supply
Supply
Supply
Supply
—
Table 7
Symbol
Input/Output Functional Description
Type
Function
相關(guān)PDF資料
PDF描述
HYB18T512800AC-5 M39012 MIL RF CONNECTOR
HYB18T512800AC DDR2 Registered Memory Modules
HYB18T512800AF DDR2 Registered Memory Modules
HYB18T512800AF-37 512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512800AF-5 512-Mbit Double-Data-Rate-Two SDRAM
相關(guān)代理商/技術(shù)參數(shù)
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