參數(shù)資料
型號: HYB18T512160AF-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 72/117頁
文件大?。?/td> 2102K
代理商: HYB18T512160AF-3S
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
72
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
Figure 58
Active Power-Down Mode Entry and Exit Example after a Write Command with AP
WL = 2, WR = 3, BL = 4
Note:Active Power-Down mode exit timing
t
XARD
(“fast exit”) or
t
XARDS
(“slow exit”) depends on the programmed
state in the MR, address bit A12. WR is the programmed value in the MRS mode register.
Figure 59
Precharge Power Down Mode Entry and Exit
Note:"Precharge" may be an external command or an internal precharge following Write with AP.
NOP
NOP
W RITE
w/AP
T0
T2
T1
T3
T4
T5
T6
T7
CMD
DQ
DQS,
DQS
NOP
NOP
NOP
NOP
NOP
NOP
Tn
Tn+1
CKE
WL = RL - 1 = 2
WL + BL/2 + WR
NOP
NOP
Act.PD 3
WR
tIS
Tn+2
tIS
Valid
Command
Active
Power-Down
Exit
tXARD or
tXARDS *)
CK, CK
DIN A0 DIN A1 DIN A2 DIN A3
Active
Power-Down
Entry
tXP
NOP
NOP
Precharge
T0
T2
T1
CMD
NOP
NOP
Tn
Tn+1
CKE
Precharge
Power-Down
Entry
NOP
NOP
tIS
Tn+2
tIS
Precharge
Power-Down
Exit
Valid
Command
tRP
NOP
T3
CK, CK
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