參數(shù)資料
型號： HYB18T512160AF-3S
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 110/117頁
文件大?。?/td> 2102K
代理商： HYB18T512160AF-3S
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Data Sheet
110
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1125
8.3.5
Setup (
t
IS
) and Hold (
t
IH
) Time Derating Tables
1. For all input signals the total input setup time and
input hold time required is calculated by adding the
data sheet value to the derating value respectively.
Example:
t
IS
(total setup tine) =
t
IS
(base) +
t
IS
2. For slow Slew Rate the total setup time might be
negative (i.e. a valid input signal will not have
reached
V
IH(ac)
/
V
IL(ac)
at the time of the rising clock)
a valid input signal is still required to complete the
transition and reach
V
IH(ac)
/
V
IL(ac)
. For Slew Rates
in between the values listed in the next tables, the
derating values may be obtained by linear
interpolation. These values are not subject to
production test. They are verified only by design
and characterization.
Table 57
Command / Address Slew Rate
(V/ns)
Derating Values for Input Setup and Hold Time (DDR2-667)
CK, CK Differential Slew Rate
2.0 V/ns
t
IS
+150
+143
+133
+120
+100
+67
0
–5
–13
–22
–34
–60
–100
–168
–200
–325
–517
–1000
Unit
Note
1.5 V/ns
t
IS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
–4
–30
–70
–138
–170
–295
–487
–970
1.0 V/ns
t
IS
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
0
–40
–108
–140
–265
–457
–940
t
IH
+94
+89
+83
+75
+45
+21
0
t
IH
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1095
t
IH
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1065
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1)2)
1) For all input signals
t
IS
(total) =
t
IS
(base) +
t
IS
and
t
IH
(total) =
t
IH
(base) +
t
IH
2) For slow slewrate the total setup time might be negative (i.e. valid input signal will not have reached V
IH(ac)
/ V
IL(ac)
at the
time of the rising clock) a valid signal is still required to complete the transistion and reach V
IH(ac)
/ V
IL(ac)
. For slew rates in
between the values listed in the next tables, the derating values may be obtained by linear interpolation. These values are
not subject to production test. They are verified only by design and characterisation.
1)
1)
1)
1)
1)
1)
1)
1)
1)
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相關(guān)PDF資料
PDF描述
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AF-3 512-Mbit DDR2 SDRAM
HYB18T512800AF-3.7 512-Mbit DDR2 SDRAM
HYB18T512800AF-3S 512-Mbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
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