參數(shù)資料
型號: HYB18T512160AF-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 41/117頁
文件大小: 2102K
代理商: HYB18T512160AF-3S
Data Sheet
41
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
ODT timing modes
Depending on the operating mode asynchronous or
synchronous ODT timings apply.
Asynchronous ODT timings (
t
AOFPD
,
t
AONPD
) apply when
the on-die DLL is disabled.
These modes are:
Slow Exit Active Power Down Mode (with MRS bit
A12 is set to “1”)
Precharge Power Down Mode
Synchronous ODT timings (
t
AOND
,
t
AOFD
,
t
AON
,
t
AOF
)
apply for all other modes.
Figure 13
ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings)
Note:
1. Synchronous ODT timings apply for Active Mode
and Standby Mode with CKE HIGH and for the
“Fast Exit” Active Power Down Mode (MRS bit A12
set to “0”). In all these modes the on-die DLL is
enabled.
2. ODT turn-on time (
t
AON.MIN
) is when the device
leaves high impedance and ODT resistance begins
to turn on. ODT turn on time max. (
t
AON.MAX
) is when
the ODT resistance is fully on. Both are measured
from t
AOND
.
3. ODT turn off time min. (
t
AOF.MIN
) is when the device
starts to turn off the ODT resistance.ODT turn off
time max. (
t
AOF.MAX
) is when the bus is in high
impedance. Both are measured from
t
AOFD
.
CKE
DQ
ODT01
ODT
CK, CK
Rtt
tAOF(min)
tAON(min)
tAON(max)
tAOF(max)
tAOND (2 tck)
tAOFD (2.5 tck)
t
IS
t
IS
T0
T1
T2
T3
T4
T5
T6
T7
T8
IS
t
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