參數(shù)資料
型號(hào): HYB18RL25632AC-5
英文描述: ?256M (8Mx32) 200MHz ?
中文描述: ?256M(8Mx32)200MHz的?
文件頁(yè)數(shù): 6/36頁(yè)
文件大小: 869K
代理商: HYB18RL25632AC-5
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 6
Infineon Technologies
This specification is preliminary and subject to change without notice
1.2
General Description
The Infineon 256M Reduced Latency DRAM (RLDRAM) contains 8 banks x 32 Mb of memory accessible
with 32bit or 16bit I/O’s in a double data rate (DDR) format where the data is provided and synchronized with
a differential echo clock signal. RLDRAM does not require row/column address multiplexing and is optimized
for fast random access and high data bandwidth.
RLDRAM is designed for communication data storages like transmit or receive buffers in telecommunication
systems as well as data or instruction cache applications requiring large amounts of memory.
1.3
Ball Configuration Package and Ballout
Figure 1
T-FBGA 144 package 256 Mbit DDR Reduced Latency DRAM
Note: All dimensions in mm
3
BOTTOM VIEW
4
0.8
8.8
11
1
1
1
12
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8
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4
2
1
A
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C
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J
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1.20 max
SIDE VIEW
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