參數(shù)資料
型號(hào)： HYB18RL25632AC-5
英文描述： ?256M (8Mx32) 200MHz ?
中文描述： ？256M（8Mx32）200MHz的？
文件頁(yè)數(shù)： 17/36頁(yè)
文件大?。?/td> 869K
代理商： HYB18RL25632AC-5
HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 17
Infineon Technologies
This specification is preliminary and subject to change without notice
2.4
Configuration Table
The following table shows, for different operating frequencies, the different RLDRAM configurations that can
be programmed into the Mode Register. The Read Latency (tRL) and the Write Latency (tWL) used by the
RLDRAM for the two Burst Lengths (BL) are also indicated. Finally the minimum row cycle time (tRC) in clock
cycles and in ns are shown as well. The shaded areas correspond to configurations that are not allowed.
Note: 1: The speed sort -3.3 provides parts functional up to 300MHz in the configuration 4 only. The functionality of the configurations
1,2 and 3 is not guaranteed for speed sort -3.3.
Note: 2: The speed sort -4.0 provides parts functional up to 250MHz in the configurations 3 and 4 only. The functionality of the
configurations 1 and 2 is not guaranteed for speed sort -4.0.
Note: 3: The speed sort -5.0 provides parts functional in all configurations.
Table 8
RLDRAM configuration table
Configuration
Frequency
Unit
1
2
3
4
tRC
cycles
5
6
7
8
tRL
cycles
5
5
5
6
tWL (BL2)
cycles
2
2
2
3
tWL (BL4)
cycles
1
1
1
2
300 MHz (-3.3)
tRC
ns
26.7
tRL
ns
20
tWL (BL2)
ns
10
tWL (BL4)
ns
6.7
250 MHz (-4.0)
tRC
ns
28.0
32.0
tRL
ns
20.0
24.0
tWL (BL2)
ns
8.0
12.0
tWL (BL4)
ns
4.0
8.0
200 MHz (-5.0)
tRC
ns
25.0
30.0
35.0
40.0
tRL
ns
25.0
25.0
25.0
30.0
tWL (BL2)
ns
10.0
10.0
10.0
15.0
tWL (BL4)
ns
5.0
5.0
5.0
10.0
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