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參數(shù)資料
| 型號(hào)： | HYB18RL25632AC-5 |
| 英文描述： | ?256M (8Mx32) 200MHz ? |
| 中文描述： | ？256M（8Mx32）200MHz的？ |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 869K |
| 代理商： | HYB18RL25632AC-5 |
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HYB18RL25616/32AC
256 Mbit DDR Reduced Latency DRAM
Version 1.42
Page 18
Infineon Technologies
This specification is preliminary and subject to change without notice
2.5
Writes (WR)
2.5.1
Write accesses are initiated with a WRITE command, as shown in
Figure 11. Row and bank addresses are provided together with the
WRITE command.
During WRITE commands, data will be registered at both edges of CK
according to the programmed burst length BL. The first valid data is
registered with the first rising CK edge WL (Write Latency) cycles after
the WRITE command has been issued.
Any WRITE burst may be followed by a subsequent READ command.
Figure 17 and Figure 18 illustrate the timing requirements for a WRITE
followed by a READ for a burst of 2 and 4 respectively.
Setup and hold time for incoming DQs relative to the CK edges are
specified as tDS and tDH.
The first or the second part of the incoming data burst is masked if the
corresponding DMx signal is sampled HIGH along with the WRITE
command. Setup and hold time for DM is the same as for addresses
and commands.
Write - Basic Information
Figure 12 Basic Write Burst Timing
Table 9
WRITE Timing Parameters
Note: 1. All timings are measured relatively to the crossing point of CK/CK# and to the crossing point with VREF of the Command and
Address signals.
Note: 2. The signal imput slew rate must be 1V/ns.
Note: 3. CK/CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially).
Parameter
Symbol
-3.3
-4.0
-5.0
Units
Notes
min
max
min
max
min
max
Data-in to CK Setup Time
t
DS
0.5
–
0.5
–
0.5
–
ns
Data-in to CK Hold Time
t
DH
0.5
–
0.5
–
0.5
–
ns
CK#
CK
BA[2:0]
A
BA
A:
BA:
DM:
Address
Bank Address
Data Mask
Don't Care
CS#
WE#
REF#
A[19:0]
DM
DM[1:0]
AS#
Figure 11
Write command
DQ
Don't Care
D0
D1
D2
D3
CK#
CK
Write Latency
t
DH
t
DS
t
DH
t
DS
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