參數(shù)資料
型號: HY62LF16206A
廠商: Hynix Semiconductor Inc.
英文描述: 128Kx16bit full CMOS SRAM
中文描述: 128Kx16bit充分的CMOS的SRAM
文件頁數(shù): 7/11頁
文件大小: 283K
代理商: HY62LF16206A
HY62LF16206A-LT12C
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
WRITE CYCLE 2 (1,4,8) (/CS1, CS2 Controlled)
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition with CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured
200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
Rev.05 /Apr. 2002
6
Data Valid
ADDR
Data
Out
/CS1
CS2
/UB,/LB
/WE
tWC
tCW
tWR(2)
tBW
tAW
tWP
Data In
High-Z
tAS
tWHZ(3,7)
tDW
tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/CS1
CS2
/UB,/LB
/WE
tWC
tCW
tWR
(2)
tBW
tAW
tWP
Data In
tDW
tDH
High-Z
High-Z
tAS
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