參數(shù)資料
型號(hào): HY62LF16206A
廠商: Hynix Semiconductor Inc.
英文描述: 128Kx16bit full CMOS SRAM
中文描述: 128Kx16bit充分的CMOS的SRAM
文件頁數(shù): 6/11頁
文件大?。?/td> 283K
代理商: HY62LF16206A
HY62LF16206A-LT12C
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
READ CYCLE 2(Note 2,3,4)
Rev.05 /Apr. 2002
5
READ CYCLE 3(Note 1,2,4)
/CS1
/UB, /LB
ADDR
Data
Out
tRC
tAA
Data Valid
Previous Data
tOH
tOH
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1, a high CS2 and low /UB
and/or /LB.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
CS2
Data Valid
High-Z
ADDR
Data
Out
tRC
/CS1
CS2
/UB ,/ LB
/OE
tAA
tACS
tBA
tOE
tCLZ
(3)
tBLZ
(3)
tOLZ
(3)
tOH
tCHZ
(3)
tBHZ
(3)
tOHZ
(3)
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參數(shù)描述
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