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參數(shù)資料
| 型號： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發(fā)生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導和語音合成器和音發(fā)生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發(fā)生器） |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
19
June 7, 2000
Audio output and volume control
The VDS84 series provide two 12-bits current
type DAC devices for driving external 8 ohm
speaker through an external NPN transistor.
The programmer must write the voice data to
the register PDAL (20H/24H) and PDAH
(21H/25H). Only 12 bits which include the high
nibble of PDALand the whole byte of PDAH are
used. The correct procedure for DAC output as
below , high nibble data of PDAL must be writ-
ten at first, and then the PDAH data is written
second.
There are 16 scales of volume controllable level
that are provided for the current type DAC out-
put. The programmer only writes the volume
control data to the VOL register (22H/26H).
The VOL1 (22H) control PDA1H-PDA1L and
VOL2 (26H) control PDA2H-PDA2L. Only the
high nibble of VOL are used. Note that writing
0H to the high nibble of VOL doesn't denote
mute output , this mean still leakage from AUD
pin through external NPN transistor , and ex-
ternal 8 ohm speaker leak current too. Only
load 00h to PDAH-PDAL will turn off DAC and
prevent leakage
Sampling rate counter
SR1, SR2, TMRC
The VDS84 series offer two sampling rate coun-
ter SR1(23H) and SR2 (27H). Those counters
contain an 8-bit programmable count-up coun-
ter. The sampling rate counter clock source is
decided by the TMRC (1DH) control register.
The TMRC defines the sampling rate counter
clock source as shown in the table below:
TMRC (1DH)
SR0 Clock Source
Bit3 Bit2 Bit1 Bit0
0
0
0
Disable counter
0
0
1
1 instruction clock /1
0
1
0
1 instruction clock /2
0
1
1
1 instruction clock /4
1
0
0
1 instruction clock /8
1
0
1
1instructionclock/16
1
1
0
1instructionclock/32
1
1
1
1instructionclock/64
TMRC (1DH)
SR1 Clock Source
Bit7 Bit6 Bit5 Bit4
0
0
0
Disable counter
0
0
1
1 instruction clock /1
0
1
0
1 instruction clock /2
0
1
1
1 instruction clock /4
1
0
0
1 instruction clock /8
1
0
1
1instructionclock/16
1
1
0
1instructionclock/32
1
1
1
1instructionclock/64
Note: One instruction clock equate one system
clock divided by 4
TMRC bit3 and bit7 are unused
Two physical registers are mapped to SR1 loca-
tion; writing SR1 makes the starting value be
placed in the counter preload register and read-
ing SR1/2 gets the contents of the counter.
When the counter (reading SR1/2) is read, the
clock will be blocked to avoid errors. As clock
blocking may result in a counting error, this
must be taken into consideration by the pro-
grammer.
! '( 2
/ " #
$ 1
! '( 7
/ , #
$ 1
& 7 ' (
/ , #
$ 1
! .
' ' # "
& % # & "
Audio output diagram
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