參數(shù)資料
型號: HTVDS84
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器,帶宏指令、聲話音成器和聲音發(fā)生器)
中文描述: 8位高性能微控制器,帶有宏觀指導(dǎo)和語音合成器和音發(fā)生器(高性能,8位微控制器,帶宏指令,聲話音成器和聲音發(fā)生器)
文件頁數(shù): 11/44頁
文件大?。?/td> 275K
代理商: HTVDS84
HTVDS84
11
June 7, 2000
Functional Description
Executive flow
The system clock for the VDS84 series is de-
rived from an RC type of oscillator. The clock is
internally divided into four non-overlapping
clocks denoted by P1, P2, P3 and P4. An in-
struction cycle consists of T1~T4.
Instruction fetching and execution are
pipelined in such a way that a fetch takes an in-
struction cycle while decoding and execution
take the next instruction cycle. The pipelining
scheme causes each instruction to execute ef-
fectively in a cycle. If an instruction changes
the program counter, two cycles are required to
complete that instruction.
Program counter
PC
The 11-bit program counter (PC) controls the
sequenceinwhichtheinstructionsstoredinthe
program ROM are executed and the ROM space
are 2048 14 bits. The contents of the program
counterareincrementedbyoneafteraprogram
memorywordisaccessedtofetchaninstruction
code. The program counter then points to a
memory word containing the next instruction
code.
The PC manipulates a program transfer by
loading the address corresponding to each in-
struction when executing a jump instruction,
conditional skip execution, loading PCL regis-
ter, subroutine call, initial reset, internal inter-
rupt or return from subroutine.
The conditional skip is activated by instruc-
tions. Once the condition is satisfied, the next
instruction, fetched during the current instruc-
tion execution, is discarded and a dummy cycle
replaces it to get a proper instruction. Other-
wise, the system will proceed with the next in-
structions.
Once a control transfer takes place, the execu-
tion requires an additional dummy cycle.
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
PC
PC+1
PC+2
System Clock
OSC (RC only)
PC
P1
P2
P3
P4
Internal
Phase
Clocks
Executive flow
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