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參數(shù)資料
| 型號(hào)： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發(fā)生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導(dǎo)和語音合成器和音發(fā)生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發(fā)生器） |
| 文件頁數(shù)： | 17/44頁 |
| 文件大小： | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
17
June 7, 2000
No. Interrupt Source Priority
Vector
a
Time-base counter
1
04H
b
Sampling rate 1
counter
2
08H
c
Sampling rate 2
counter
3
0CH
TABLE of the interrupt priority
The sampling rate 1 counter interrupt request
flag (FS2), sampling rate 0 counter interrupt
request flag (FS1), Timebase interrupt request
flag (F1MS), enable sampling rate 1 counter bit
(SR2I), enable sampling rate 0 counter bit
(SR1I), enable Timebase bit (ETBI,STE) and
enable master interrupt bit (EMI) make up an
interrupt control register (INTC) which is lo-
cated at 0BH in the data memory. EMI, ETBI,
SBMI, SR1I and SR2I are used to control the
enable/disable status of interrupts. These bits
prevent the requested interrupt from being ser-
viced. Once the interrupt request flags (F1MS,
FS1, FS2) are all set, they will remain in the
INTC register till the interrupts are serviced or
cleared by a software instruction.
The "CALL subroutine" is preferably not used
within the interrupt subroutine. This is be-
cause interrupts often occur in an unpredict-
able manner or required to be serviced
immediately in certain applications. If only one
stack is left and enabling the interrupt is not
well controlled, operation of the "call" in the in-
terrupt subroutine will damage the original
control sequence.
Oscillator configuration
The VDS84 provides RC oscillator circuits, for
system clocks. When the device enters the HALT
mode, the system oscillator stops to conserve
power. An external resistor between OSC and
GND is required and the range of the resistance
has to be from 91K to 180K. The RC type of oscil-
lator provides the most cost-effective solution.
Nonetheless, the frequency of the oscillation may
vary with VDD, temperature and the chip itself
duetoprocessvariations.Itis,therefore,notsuit-
able for timing sensitive operations where an ac-
curate oscillator frequency is required.
Watchdog Timer
WDT
The WDT clock source is implemented by an in-
struction clock (system clock divided by 4). The
Watchdog Timer is designed to prevent soft-
ware malfunction or sequence jumping to an
unknown location with unpredictable results.
Itcanbedisabledbymaskoption.Afteritisdis-
abled, all executions related to WDT are ig-
nored. WDT is first divided by 4096 (12 stages)
to get a nominal time-out period of 1ms (under
Fsys=4MHz) once an internal WDT oscillator is
selected. Then the WDT register is divided by 7,
so the WDT time-out period is 7ms (under
Fsys=4MHz). ( See the Fig. Sampling counter
and Timebase and IRQ Diagram)
The WDT overflow under a normal operation
initializes a "chip reset" and sets the status bit
"TO" It will initialize a "warm reset", and only
PC and SP are reset to zero. To clear the con-
tents of the WDT register, two methods are
adopted, namely, software instructions, and
"HALT" instruction. The software instructions
include "CLR WDT" and the other sets - "CLR
WDT1" and "CLR WDT2". Of these two types of
instructions, by mask option only one can be ac-
tive at a time . If "CLR WDT" is chosen (i.e.,
"one instruction" selected), any execution of the
"CLR WDT" instruction will clear the WDT.
In the case that "CLR WDT1" and "CLR WDT2"
are selected (i.e., "two instruction" selected) ,
these two instructions must be executed to
clear the WDT; otherwise WDT may reset the
chip as a result of time-out.
Oscillator
OSC
R
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