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參數(shù)資料
| 型號： | HTVDS84 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance Microcontroller With Macro Instruction and Voice Synthesizer and Tone Generator(高性能、8位微控制器，帶宏指令、聲話音成器和聲音發(fā)生器) |
| 中文描述： | 8位高性能微控制器，帶有宏觀指導(dǎo)和語音合成器和音發(fā)生器（高性能，8位微控制器，帶宏指令，聲話音成器和聲音發(fā)生器） |
| 文件頁數(shù)： | 16/44頁 |
| 文件大小： | 275K |
| 代理商： | HTVDS84 |
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HTVDS84
16
June 7, 2000
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clearing
the EMI bit). This scheme may prevent any fur-
ther interrupt nesting. Other interrupt re-
quests may happen during this interval but
only the interrupt request flag is recorded. If an
interrupt needs servicing within the service
routine, the programmer may set the EMI bit
and the corresponding bit of INTC, allowing in-
terrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged until the
SP is decremented, whether or not the related
interrupt is enabled. If immediate service is de-
sired, the stack has to be prevented from be-
coming full.
As an interrupt is serviced, a control transfer
occurs by pushing the program counter onto the
stack and then branching to subroutines at the
specified location(s) in the program memory.
Only the program counter is pushed onto the
stack. The programmer must save the contents
of the register or status register (STATUS) in
advance if they are altered by an interrupt ser-
vice program which corrupts the desired con-
trol sequence.
Timebase interrupt is triggered by a 3-stage
counter overflow. The related interrupt request
flag (F1MS; bit 4 of INTC) are set . When re-
lated control bits are enabled (EMI,ETBI=1
and STE=0 ) , the stack is not full and the
Timebase interrupt is active, a subroutine call
to location 04H will occur. The interrupt re-
quest flag (F1MS) and EMI bits will be cleared
automatically to disable other interrupts.
The sampling rate counter interrupt is initial-
ized by setting a sampling rate counter inter-
rupt request flag (FS1/FS2; bit 5/6 of INTC),
which is caused by the counter overflow.
When the related control bits are enabled
(EMI,SR1I/SR2I=1), the stack is not full and
the sampling rate interrupt is active, a sub-
routine call to location 08H/0CH will occur.
The related interrupt request flag (FS1/FS2)
and the EMI bit will be cleared automatically
to disable further interrupts.
During the execution of an interrupt subrou-
tine, other interrupt acknowledgments are all
held until the "RETI" instruction is executed or
the EMI bit and the related interrupt control
bit are set to 1 (if the stack is not full). To return
from an interrupt subroutine, "RET" or "RETI"
may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
Interrupts occurring in an interval between the
risingedgesoftwoconsecutiveT2pulseswillbe
serviced at the latter of the two T2 pulses if the
corresponding interrupts are enabled. In the
case of simultaneous requests, they can be
masked by resetting the EMI bit. The Priority
table illustrates the priority of applying the si-
multaneous requests:
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt (1: enable; 0: disable)
1
ETBI
Controls the Timebase interrupt (solve) (1: enable; 0: disable)
2
ES1I
Controls the Sampling rate counter 1 interrupt
(1: enable; 0: disable)
3
ES2I
Controls the Sampling rate counter 2 interrupt
(1: enable; 0: disable)
4
F1MS
Timebase counter request flag (1: active; 0: inactive)
5
FS1
Sampling rate counter 1 request flag (1: active; 0: inactive)
6
FS2
Sampling rate counter 2 request flag (1: active; 0: inactive)
7
STE
Controls the Timebase interrupt (master) (1: disable; 0: enable)
INTC register
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