HT82K96A
Rev. 1.50
22
August 25, 2006
MCU can communicate with endpoint FIFO by setting the corresponding registers, of which address is listed in the fol-
lowing table. After reading current data, next data will show on after 2 s. using to check endpoint FIFO status and re-
sponse to MISC register, if read/write action is still going on.
Registers
R/W
Bank
Address
Bit7~Bit0
FIFO0
R/W
1
48H
Data7~Data0
FIFO1
R/W
1
49H
Data7~Data0
FIFO2
R/W
1
4AH
Data7~Data0
FIFO3
R/W
1
4BH
Data7~Data0
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,
writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing
and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H
check not ready (01H)
01H
delay 2 s, check 41H
read* from FIFO0 register and
03H
02H
Write FIFO1 sequence
0AH
check not ready (0BH)
0BH
delay 2 s, check 4BH
09H
write* to FIFO1 register and
08H
Check whether FIFO0 can be read or not
00H
01H
delay 2 s, check 41H (ready) or 01H (not ready)
00H
Check whether FIFO1 can be written or not
0AH
0BH
delay2 s,check4BH(ready)or0BH(notready)
0AH
Read 0-sized packet sequence form FIFO0
00H
01H
delay 2 s, check 81H
read once (01H)
03H
02H
Write 0-sized packet sequence to FIFO1
0AH
0BH
delay 2 s, check 0BH
0FH
0DH
08H
Note:
*: There are 2 s existing between 2 reading action or between 2 writing action
The definitions of the USB/PS2 status and control register (USC; 1AH) are as shown.
Bit No.
Label
R/W
Function
0
SUSP
R
Read only, USB suspend indication. When this bit is set to 1 (set by SIE), it indi-
cates the USB bus enters suspend mode. The USB interrupt is also triggered on any
changing of this bit.
1
RMWK
W
USB remote wake up command. It is set by MCU to force the USB host leaving the
suspend mode. When this bit is set to 1 , 2 s delay for clearing this bit to 0 is
needed to insure the RMWK command is accepted by SIE.
2
URST
R/W
USB reset indication. This bit is set/cleared by USB SIE. This bit is used to detect
which bus (PS2 or USB) is attached. When the URST is set to 1 , this indicates a
USB reset is occurred (The attached bus is USB) and a USB interrupt will be initial-
ized.
3
RESUME
R
USB resume indication. When the USB leaves suspend mode, this bit is set to 1
(set by SIE). This bit will appear 20ms waiting for MCU to detect. When the RESUME
is set by SIE, an interrupt will be generated to wake-up the MCU. In order to detecting
the suspend state, MCU should set USBCKEN and clear SUSP2 (in SCC register) to
enable the SIE detecting function. The RESUME will be cleared while the SUSP is
going
0 . When MCU is detecting the SUSP, the RESUME (causes MCU to
wake-up) should be remembered and taken into consideration.
4
PS2DAI
R
Read only, USBD-/DATA input
5
PS2CKI
R
Read only, USBD+/CLK input
6
PS2DAO
W
Data for driving USBD-/DATA pin when work under 3D PS2 mouse function.
(Default= 1 )
7
PS2CKO
W
Data for driving USBD+/CLK pin when work under 3D PS2 mouse function.
(Default= 1 )
USC (1AH) Register