參數(shù)資料
型號: HT82K96A
廠商: Holtek Semiconductor Inc.
英文描述: USB Multimedia Keyboard Encoder 8-Bit Mask MCU
中文描述: 的USB多媒體鍵盤編碼器8位微控制器面膜
文件頁數(shù): 21/46頁
文件大小: 298K
代理商: HT82K96A
HT82K96A
Rev. 1.50
21
August 25, 2006
SIES. Register (for version C or later version) is used to indicate the present signal state which the SIE receives and
also defines whether the SIE has to change the device address automatically.
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Func.
Reserved bit
F0_ERR
Adr_set
R/W
R/W
R/W
Reg_Adr
01000101B
Note: Bit7 must be 0
Func. Name
R/W
Description
Adr_set
R/W
This bit is used to configure the SIE to automatically change the device address with
the value of the Address+Remote_WakeUp Register (42H).
Whenthisbitissetto 1 byF/W,theSIEwillupdatethedeviceaddresswiththevalue
of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully
readthedatafromthedevicebytheINoperation.TheSIEwillclearthebitafterupdat-
ing the device address. Otherwise, when this bit is cleared to 0 , the SIE will update
the device address immediately after an address is written to the Address+Re-
mote_WakeUp Register (42H)
Default 0
F0_Err
R/W
ThisbitisusedtoindicatethatsomeerrorshaveoccurredwhenaccessingtheFIFO0.
This bit is set by SIE and cleared by F/W.
Default 0
SIES (45H) Register Table
MISC register combines a command and status to control desired endpoint FIFO action and to show the status of
wanted endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No.
Label
R/W
Function
0
REQ
R/W
After setting other status of desired one in the MISC, endpoint FIFO can be requested
by setting this bit to 1 . After job has been done, this bit has to be cleared to 0
1
TX
R/W
This bit defines the direction of data transferring between MCU and endpoint FIFO.
When the TX is set to 1 , this means that MCU wants to write data to endpoint FIFO.
After the job has been done, this bit has to be cleared to 0 before terminating re-
quest to represent end of transferring. For reading action, this bit has to be cleared to
0 to represent that MCU wants to read data from endpoint FIFO and has to be set to
1 after the job done.
2
CLEAR
R/W Clear the requested endpoint FIFO, even the endpoint FIFO is not ready.
4
3
SELP1
SELP0
R/W
To define which endpoint FIFO is selected, SELP1,SELP0:
00: endpoint FIFO0
01: endpoint FIFO1
10: endpoint FIFO2
11: endpoint FIFO3
5
SCMD
R/W
It is used to show that the data in endpoint FIFO is SETUP command. This bit has to
be cleared by firmware. That is to say, even the MCU is busing, the device will not
miss any SETUP commands from host.
6
READY
R
Readonlystatusbit,thisbitisusedtoindicatethatthedesiredendpointFIFOisready
to work.
7
LEN0
R/W
It is used to indicate that a 0-sized packet is sent from host to MCU. This bit should be
cleared by firmware.
MISC (46H) Register
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