HT82A850R
Rev. 1.10
24
July 25, 2007
Label
Functions
WCOL
Set by SIO cleared by users
CESN
Enable or disable device selection function pin
Master mode: 1/0=with/without SCS output control
Slave mode: 1/0= with/without SCS input control
SBEN
Enable or disable serial bus (0= initialize all status flags)
When SBEN=0, all status flags should be initialized
When SBEN=0, all SIO related function pins should stay in a floating state
TRF
1= data transmitted or received
0= data is transmitting or still not received
If the clock polarity set to rising edge (SIO_CPOL=1), the serial clock timing will follow CLK, otherwise (SIO_CPOL=0)
CLK is the serial clock timing.
Mode Control
The MODE_CTRL register is used to control the DAC and ADC operational mode and the SPI function.
Bit No.
Label
Functions
0
DA_L_ENB
DAC enable/disable control (left channel)
1= DAC Left Channel disable
0= DAC Left Channel enable (default)
1
DA_R_ENB
DAC enable/disable control (right channel)
1= DAC Right Channel disable
0= DAC Right Channel enable (default)
2
AD_ENB
ADC enable/disable control
1= ADC power down
0= ADC power on (default)
3
PLAY_MODE
DAC play mode control
1= 8kHz/16-bit
0= 48kHz/16-bit (default)
4
SIO_CPOL
There are three bits used to control the mode of SPI operation.
1= clock polarity rising edge
0= clock polarity falling edge (default)
5
SIO_WCOL
1= WCOL bit of SBCR register enable
0= WCOL bit of SBCR register disable (default)
6
SIO_CSEN
1= CSEN bit of SBCR register enable
0= CSEN bit of SBCR register disable (default)
7
Undefined bit, read as 0
MODE_CTRL (34H) Register
SPI Usage Example
SPI_Test:
clr
set
clr
;Master Mode, SCLK=fSIO
clr
M1
clr
M0
;--------------
clr
CKS
clr
TRF
clr
TRF_INT
set
MLS
set
CSEN
set
SBEN
UCC.@UCC_SYSCLK
SIO_CSEN
SIO_CPOL
;12MHz SYSCLK
;SPI chip select function enable
;falling edge change data
;f
SIO
=f
SYS
/2
;clear TRF flag
;clear interrupt SPI flag
;MSB shift first
;Chip select enable
;SPI enable, SCS will go low