參數(shù)資料
型號(hào): HT82A850R
廠商: Holtek Semiconductor Inc.
英文描述: Audio MCU
中文描述: 音頻控制器
文件頁數(shù): 14/41頁
文件大?。?/td> 296K
代理商: HT82A850R
HT82A850R
Rev. 1.10
14
July 25, 2007
The registers status are summarised in the following table.
Register
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT Time-Out
(HALT)*
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Program
Counter
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
USVC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
INTC1
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
UCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
DAC_LIMIT_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAC_LIMIT_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAC_WR
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PGA_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PFDC
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PFDD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
MODE_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0uuu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECOED_
DATA_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
RECOED_
DATA_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note:
* stands for warm reset
u stands for unchanged
x stands for unknown
_ stands for undefined
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