HT82A850R
Rev. 1.10
12
July 25, 2007
Power Down Operation
The Power-down mode is entered by the execution of a
HALT instruction and results in the following:
The system oscillator will be turned off but the WDT
oscillator keeps running if the internal WDT oscillator
is selected.
The contents of the on-chip data memory and regis-
ters remain unchanged.
The WDT and WDT prescaler will be cleared and will
start counting again if the WDT clock is sourced from
the internal WDT oscillator.
All of the I/O ports remain in their original condition.
The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port Aor a WDToverflow. An external re-
set causes a device initialisation and the WDT overflow
performs a warm reset . After the TO and PDF flags
are examined, the cause for the device reset can be de-
termined. The PDF flag is cleared by a system power-up
or by executing the CLR WDT instruction and is set
when executing the HALT instruction. The TO flag is
set if the WDT time-out occurs, and causes a wake-up
that only resets the program counter and SP; the others
remain in their original status.
A port A wake-up and interrupt methods can be consid-
ered as a continuation of normal execution. Each pin in
port Acan be independently selected to wake-up the de-
vice using configuration options. After awakening from
an I/O port stimulus, the program will resume execution
at the next instruction. If the device is awakened from an
interrupt, two sequence may occur. If the related inter-
rupt is disabled or the interrupt is enabled but the stack
is full, the program will resume execution at the next in-
struction. If the interrupt is enabled and the stack is not
full, the regular interrupt response takes place. If an in-
terrupt request flag is set to 1 before entering the
Power-down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 t
SYS
(system clock periods) to resume nor-
mal operation, i.e., a dummy period is inserted. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
The ADC, DAC and PAwill all be powered down when in
the HALT mode.
%
&
A ( -
> 1 5
%
%
&
+ 1 5
%
> 1
1 %
%
1
) *
.
A
&
%
Watchdog Timer
Bit No.
Label
Function
0
1
2
WS0
WS1
WS2
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, division ratio = 1:1
Bit 2,1,0 = 001, division ratio = 1:2
Bit 2,1,0 = 010, division ratio = 1:4
Bit 2,1,0 = 011, division ratio = 1:8
Bit 2,1,0 = 100, division ratio = 1:16
Bit 2,1,0 = 101, division ratio = 1:32
Bit 2,1,0 = 110, division ratio = 1:64
Bit 2,1,0 = 111, division ratio = 1:128
3
Unused bit, read as 0
7~4
T3~T0
Test mode setting bits
(T3, T2, T1, T0)=(0, 1, 0, 1), enter DAC write mode. Otherwise normal operation.
WDTS (09H) Register