HT82A850R
Rev. 1.10
21
July 25, 2007
Two registers, SBCR and SBDR, are provided for serial interface control, status and data storage.
SBCR: Serial bus control register
Bit7 (CKS): clock source selection: f
SIO
= f
SYS
/2, select as 0; f
SIO
= f
SYS
, select as 1
Bit6 (M1), Bit5 (M0): master/slave mode and baud rate selection
M1, M0=
00: Master mode, baud rate = f
SIO
01: Master mode, baud rate = f
SIO
/4
10: Master mode, baud rate = f
SIO
/16
11: Slave mode
Bit4 (SBEN): Serial bus enable/disable (1/0)
Enable: (SCS dependent on CSEN bit)
Disable
enable: SCK, SDI, SDO, SCS =0 (SCK= 0 ) and wait to write data to SBDR (TXRX buffer)
Master mode: write data to SBDR (TXRX buffer)
start transmission/reception automatically
Master mode: when data has been transferred
set TRF
Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in the TXRX buffer is shifted-out and
data on SDI is shifted-in.
Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports.
Label
Functions
SBEN=1
PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1).
SBEN=0
PC4~PC7 are general purpose I/O Port pins - default
Note: 1. If SBEN= 1 , the pull-high resistors on PC4~PC7 will be disabled. When this happens external pull-high
resistors should be added to the SPI related pins if necessary (EX: pin SCS).
2. If CSEN= 0 , the SCS pin will enter a floating state.
Bit3 (MLS): MSB or LSB (1/0) shift first control bit
Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating
Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when the data is transferring
writing will be ignored if data is written to SBDR (TXRX buffer) when the data is transferring
WCOL will be set by hardware and cleared by software.
Bit 0 (TRF): data transferred or data received
used to generate an interrupt
Note: data reception is still operational when the MCU enters the Power-down mode
SBDR: Serial bus data register
Data written to SBDR
write data to the TXRX buffer only
Data read from SBDR
read from SBDR only
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing to SBDR
Master clock sending started by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception