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參數(shù)資料
| 型號： | HT48C50- |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大小： | 295K |
| 代理商： | HT48C50- |
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HT48C50-1
14
June 14, 2000
Preliminary
If an RC oscillator is used, an external resistor
between OSC1 and VDD is required and the
resistance must range from 51k
system clock, divided by 4, is available on
OSC2, which can be used to synchronize exter-
nal logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of oscillation may vary with VDD, tempera-
tures and the chip itself due to process varia-
tions. It is, therefore, not suitable for timing
sensitive operations where an accurate oscilla-
tor frequency is desired.
to 1M . The
If the Crystal oscillator is used, a crystal across
OSC1 and OSC2 is needed to provide the feed-
back and phase shift required for the oscillator.
No other external components are required. In
stead of a crystal, a resonator can also be con-
nected between OSC1 and OSC2 to get a fre-
quency reference, but two external capacitors
in OSC1 and OSC2 are required. If the internal
RC oscillator is used, the OSC1 and OSC2 can
be selected as general I/O lines or an 32768Hz
crystal oscillator (RTC OSC). Also, the frequen-
cies of the internal RC oscillator can be
3.2MHz, 1.6MHz, 800kHz and 400kHz (de-
pends on the options).
The WDT oscillator is a free running on-chip RC
oscillator, and no external components are re-
quired.Evenifthesystementersthepowerdown
mode, the system clock is stopped, but the WDT
oscillator still works within a period of 78 s. The
WDT oscillator can be disabled by mask option to
conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a ded-
icated RC oscillator (WDT oscillator), RTC
clock or instruction clock (system clock divided
by 4), determines the mask option. This timer is
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The Watchdog
Timer can be disabled by mask option. If the
Watchdog Timer is disabled, all the executions
related to the WDT result in no operation. The
RTC clock is enabled only in the internal
RC+RTC mode.
Once the internal WDT oscillator (RC oscillator
withaperiodof65 s/5Vnormally)isselected,it
is first divided by 256 (8-stage) to get the nomi-
nal time-out period of 16.6ms/5V. This time-out
period may vary with temperatures, VDD and
process variations. By invoking the WDT
prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0
of the WDTS) can give different time-out periods.
IfWS2,WS1,andWS0areallequalto1,thedivi-
sion ratio is up to 1:128, and the maximum
time-outperiodis2.2s/5Vseconds.IftheWDTos-
cillator is disabled, the WDT clock may still come
from the instruction clock and operates in the
same manner except that in the HALT state the
WDT may stop counting and lose its protecting
purpose. In this situation the logic can only be re-
started by external logic. The high nibble and bit
3 of the WDTS are reserved for user's defined
flags, which can be used to indicate some speci-
fied status.
If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) or
32kHz crystal oscillator (RTC OSC) is strongly
recommended, since the HALT will stop the sys-
tem clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
The WDT overflow under normal operation will
initialize "chip reset" and set the status bit
"TO". But in the HALT mode, the overflow will
initialize a warm reset and only the PC and
SP are reset to zero. To clear the contents of
WDT (including the WDT prescaler), three
methods are adopted; external reset (a low level
to RES), software instruction and a "HALT" in-
struction. The software instruction include
"CLR WDT" and the other set
and"CLRWDT2".Ofthesetwotypesofinstruc-
"CLR WDT1"
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