- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385399 > HT48C50- (Holtek Semiconductor Inc.) 8-BIT MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號： | HT48C50- |
| 廠商： | Holtek Semiconductor Inc. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 13/45頁 |
| 文件大?。?/td> | 295K |
| 代理商： | HT48C50- |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
HT48C50-1
13
June 14, 2000
Preliminary
ruptisenabled,thestackisnotfullandtheT1F
is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (T1F)
will be reset and the EMI bit cleared to disable
further interrupts.
Duringtheexecutionofaninterruptsubroutine,
other interrupt acknowledge signals are held
until the "RETI" instruction is executed or the
EMI bit and the related interrupt control bit are
set to 1 (if the stack is not full). To return from
the interrupt subroutine, "RET" or "RETI" may
be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
No. Interrupt Source Priority Vector
a
External Interrupt
1
04H
b
Timer/event
Counter 0 Overflow
2
08H
c
Timer/event
Counter 1 Overflow
3
0CH
The timer/event counter 0/1 interrupt request
flag (T0F/T1F), external interrupt request flag
(EIF), enable timer/event counter 0/1 interrupt
bit (ET0I/ET1I), enable external interrupt bit
(EEI) and enable master interrupt bit (EMI)
constitute an interrupt control register (INTC)
which is located at 0BH in the data memory.
EMI, EEI, ET0I and ET1I are used to control
the enabling/disabling of interrupts. These bits
prevent the requested interrupt from being ser-
viced. Once the interrupt request flags (T0F,
T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or
cleared by a software instruction.
It is recommended that a program does not
use the "CALL subroutine" within the inter-
rupt subroutine. Interrupts often occur in an
unpredictable manner or need to be serviced
immediately in some applications. If only one
stack is left and enabling the interrupt is not
well controlled,theoriginalcontrolsequencewill
be damaged once the "CALL" operates in the in-
terrupt subroutine.
Oscillator configuration
There are 3 oscillator circuits in the
microcontroller.
All of them are designed for system clocks,
namely the external RC oscillator, the external
Crystal oscillator and the internal RC
oscillator, which are determined by mask op-
tion. No matter what oscillator type is selected,
the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an
external signal to conserve power.
& ! * = +
4 ; > # ! * !
,
*
. ; > # ! * !
4 ; ! ; *
,
* # ; !
, - ,
'
" ! #
!
,
*
Watchdog Timer
& !* #
6 ' * 1 . 3 4 A 8
*
# !
* " *
#
+
+ . " 9
System oscillator
相關PDF資料 |
PDF描述 |
|---|---|
| HT48C70-1 | I/O Type 8-Bit MCU |
| HT48R70A-1 | I/O Type 8-Bit MCU |
| HT48C70 | 8-Bit Microcontroller Series |
| HT48CA0-2 | Remote Type 8-Bit MCU |
| HT48RA0 | Remote Type 8-Bit MCU |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HT48C50(28SKDIP-H) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| HT48C50(40DIP-A) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| HT48C50-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit I/O Type Mask MCU |
| HT48C50-1_09 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
| HT48C70 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:8-Bit Microcontroller Series |
發(fā)布緊急采購，3分鐘左右您將得到回復。