HT48C50-1
9
December 19, 2000
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
Location 00CH
This location is reserved for the timer/event
counter 1 interrupt service program. If a
timer interrupt results from a timer/event
counter 1 overflow, and the interrupt is en-
abled and the stack is not full, the program
begins execution at location 00CH.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions "TABRDC
[m]" (the current page, 1 page=256 words)
and "TABRDL [m]" (the last page) transfer
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
the lower-order byte in the table is
well-defined, the other bits of the table word
are transferred to the lower portion of TBLH,
and the remaining 1-bit words are read as "0".
The Table Higher-order byte register (TBLH)
is read only. The table pointer (TBLP) is a
read/write register (07H), which indicates the
table location. Before accessing the table, the
location must be placed in the TBLP. The
TBLH is read only and cannot be restored. If
the main routine and the ISR (Interrupt Ser-
vice Routine) both employ the table read in-
struction, the contents of the TBLH in the
main routine are likely to be changed by the
table read instruction used in the ISR. Errors
can occur. In other words, using the table read
instruction in the main routine and the ISR
simultaneously should be avoided. However,
if the table read instruction has to be applied
in both the main routine and the ISR, the in-
terrupt is supposed to be disabled prior to the
table read instruction. It will not be enabled
until the TBLH has been backed up. All table
relatedinstructionsrequiretwocyclestocom-
plete the operation. These areas may function
as normal program memory depending upon
the requirements.
Stack register
STACK
This is a special part of the memory which is
used to save the contents of the program coun-
ter (PC) only. The stack is organized into 6 lev-
els and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledge signal, the contents of the program
counter are pushed onto the stack. At the end of
a subroutine or an interrupt routine, signaled
by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value
from the stack. After a chip reset, the SP will
point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be
recorded but the acknowledge signal will be in-
hibited. When the stack pointer is decremented
(by RET or RETI), the interrupt will be ser-
viced. This feature prevents stack overflow al-
lowing the programmer to use the structure
more easily. In a similar case, if the stack is full
and a "CALL" is subsequently executed, stack
overflow occurs and the first entry will be lost
(only the most recent 6 return addresses are
stored).