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參數(shù)資料
| 型號： | HT48C50-1 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器，用于多I/O接口設(shè)備) |
| 中文描述： | 8位高性能RISC架構(gòu)微控制器等的多個I / O應(yīng)用（高性能，指令類似的RISC的8位微控制器，用于多予適用/輸出接口設(shè)備） |
| 文件頁數(shù)： | 12/45頁 |
| 文件大小： | 292K |
| 代理商： | HT48C50-1 |
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HT48C50-1
12
December 19, 2000
Interrupt
The device provides an external interrupt and
internal timer/event counter interrupts. The
Interrupt Control Register (INTC;0BH) con-
tains the interrupt control bits to set the en-
able/disable and the interrupt request flags.
Once an interrupt subroutine is serviced, all
the other interrupts will be blocked (by clearing
the EMI bit). This scheme may prevent any fur-
ther interrupt nesting. Other interrupt re-
quests may occur during this interval but only
the interrupt request flag is recorded. If a cer-
taininterruptrequiresservicingwithintheser-
vice routine, the EMI bit and the corresponding
bit of the INTC may be set to allow interrupt
nesting. If the stack is full, the interrupt request
will not be acknowledged, even if the related in-
terrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must
be prevented from becoming full.
All these kinds of interrupts have a wake-up ca-
pability. As an interrupt is serviced, a control
transferoccursbypushingtheprogramcounter
onto the stack, followed by a branch to a sub-
routine at specified location in the program
memory. Only the program counter is pushed
onto the stack. If the contents of the register or
status register (STATUS) are altered by the in-
terrupt service program which corrupts the de-
sired control sequence, the contents should be
saved in advance.
External interrupts are triggered by a high to
low transition of the INT and the related inter-
ruptrequestflag(EIF;bit4ofINTC)willbeset.
When the interrupt is enabled, the stack is not
full and the external interrupt is active, a sub-
routine call to location 04H will occur. The in-
terrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
The internal timer/event counter 0 interrupt is
initialized by setting the timer/event counter 0
interrupt request flag (T0F; bit 5 of INTC),
caused by a timer 0 overflow. When the inter-
ruptisenabled,thestackisnotfullandtheT0F
bit is set, a subroutine call to location 08H will
occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable
further interrupts.
The internal timer/even counter 1 interrupt is
initialized by setting the timer/event counter 1
interrupt request flag (T1F;bit 6 of INTC),
caused by a timer 1 overflow. When the inter-
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ET0I
Controls the timer/event counter 0 interrupt
(1= enabled; 0= disabled)
3
ET1I
Controls the timer/event counter 1 interrupt
(1= enabled; 0= disabled)
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
T0F
Internal timer/event counter 0 request flag
(1= active; 0= inactive)
6
T1F
Internal timer/event counter 1 request flag
(1= active; 0= inactive)
7
Unused bit, read as "0"
INTC register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HT48C50- | 8-BIT MICROCONTROLLER |
| HT48C70-1 | I/O Type 8-Bit MCU |
| HT48R70A-1 | I/O Type 8-Bit MCU |
| HT48C70 | 8-Bit Microcontroller Series |
| HT48CA0-2 | Remote Type 8-Bit MCU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT48C50-1_09 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
| HT48C70 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:8-Bit Microcontroller Series |
| HT48C70(40DIP-A) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| HT48C70(64QFP-A) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| HT48C70-1 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:I/O Type 8-Bit MCU |
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