HT48C50-1
20
December 19, 2000
cur at the same time). When the timer/event
counter 0/1 (reading TMR0/TMR1) is read, the
clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this
mustbetakenintoconsiderationbytheprogram-
mer.
The bit0~bit2 of the TMR0C can be used to de-
fine the pre-scaling stages of the internal clock
sources of timer/event counter 0. The defini-
tions are as shown. The overflow signal of
timer/event counter 0 can be used to generate
PFD signals for buzzer driving.
Input/output ports
There are 35 bidirectional input/output lines in
the microcontroller, labeled from PA to PD and
PG, which are mapped to the data memory of
[12H], [14H], [16H], [18H] and [1EH] respec-
tively. All of these I/O ports can be used for input
andoutputoperations.Forinputoperation,these
portsarenon-latching,thatis,theinputsmustbe
ready at the T2 rising edge of instruction "MOV
A,[m]" (m=12H, 14H, 16H, 18H or 1EH). For out-
putoperation,allthedataislatchedandremains
unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC,
PBC, PCC, PDC, PGC) to control the input/out-
put configuration. With this control register,
CMOS output or schmitt trigger input with or
without pull-high resistor structures can be re-
configured dynamically (i.e. on-the-fly) under
software control. To function as an input, the
corresponding latch of the control register must
write "1". The input source also depends on the
control register. If the control register bit is "1",
the input will read the pad state. If the control
register bit is "0", the contents of the latches
will move to the internal bus. The latter is pos-
sible in the "read-modify-write" instruction.
For output function, CMOS is the only configu-
ration. These control registers are mapped to
locations 13H, 15H, 17H, 19H and 1FH.
* ,
# ' ! )
!
' * !
3 * / # !
#@ ! * !
' * #!
!* /
'
@
! *! !
+
= * " ! #
3 * / # !
#@ ! * !
6
( 8
( B * / & !
/
Timer/event counter 1
Label (TMR1C)
Bits
Function
0~2
Unused bit, read as"0"
TE
3
To define the TMR1 active edge of timer/event counter 1
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer 1 counting
(0=disabled; 1=enabled)
5
Unused bit, read as"0"
TM0
TM1
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C register