參數(shù)資料
型號(hào): HT48C50-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個(gè)I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁(yè)數(shù): 21/45頁(yè)
文件大小: 292K
代理商: HT48C50-1
HT48C50-1
21
December 19, 2000
After a chip reset, these input/output lines re-
main at high levels or floating state (depending
on the pull-high options). Each bit of these in-
put/outputlatchescanbesetorclearedby"SET
[m].i" and "CLR [m].i" (m=12H, 14H, 16H, 18H
or 1EH) instructions.
Some instructions first input data and then fol-
low the output operations. For example, "SET
[m].i", "CLR [m].i", "CPL [m]", "CPLA[m]" read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accu-
mulator.
Each line of port A has the capability of wak-
ing-up the device. The highest 5-bit of port G are
not physically implemented; on reading them a
"0" is returned whereas writing then results in
no-operation. See Application note.
There is a pull-high option available for all I/O
lines (bit option). Once the pull-high option of
an I/O line is selected, the I/O line have
pull-high resistor. Otherwise, the pull-high re-
sistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode
will cause a floating state.
The PB0 and PB1 are pin-shared with BZ and
BZ signal, respectively. If the BZ/BZ option is
selected, the output signal in output mode of
PB0/PB1 will be the PFD signal generated by
timer/event counter 0 overflow signal. The in-
put mode always remain in its original func-
tions. Once the BZ/BZ option is selected, the
buzzer output signals are controlled by the PB0
data register only. The I/O functions of
PB0/PB1 are shown below.
PB0 I/O
I
I
O
O
O
O
O
O
O
O
PB1 I/O
I
O
I
I
I
O
O
O
O
O
PB0 Mode
x
x
C
B
B
C
B
B
B
B
PB1 Mode
x
C
x
x
x
C
C
C
B
B
PB0 Data
x
x
D
0
1
D
0
0
1
0
1
PB1 Data
x
D
x
x
x
D
1
D
D
x
x
PB0 Pad Status
I
I
D
0
B
D
0
0
B
0
B
PB1 Pad Status
I
D
I
I
I
D
1
D
D
0
B
Note: I input,
B buzzer option, BZ or BZ,
C CMOS output
O output,
D, D
0
, D
1
data,
x don't care
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