HT48C50-1
10
December 19, 2000
Data memory
RAM
The data memory is designed with 184 8 bits.
The data memory is divided into two func-
tional groups: special function registers and
general purpose data memory (160 8). Most
are read/write, but some are read only.
The special function registers include the indi-
rect addressing registers (00H, 02H),
timer/event
counter
timer/event counter 0 control register
(TMR0C;0EH), timer/event counter 1 higher
order byte register (TMR1H;0FH), timer/event
counter 1 lower order byte register
(TMR1L;10H), timer/event counter 1 control
register (TMR1C;11H), program counter
lower-order byte register (PCL;06H), memory
pointer registers (MP0;01H, MP1;03H), accu-
mulator
(ACC;05H),
(TBLP;07H), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH),
interrupt control register (INTC;0BH), Watch-
dog
Timer
option
(WDTS;09H), I/O registers (PA;12H, PB;14H,
PC;16H, PD;18H, PG;1EH) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H,
PDC;19H, PGC;1FH). The remaining space be-
fore the 60H is reserved for future expanded
usage and reading these locations will get
"00H". The general purpose data memory, ad-
dressed from 60H to FFH, is used for data and
control information under instruction com-
mands.
0
(TMR0;0DH),
table
pointer
setting
register
All of the data memory areas can handle arith-
metic, logic, increment, decrement and rotate
operations directly. Except for some dedicated
bits, each bit in the data memory can be set and
reset by "SET [m].i" and "CLR [m].i". They are
also indirectly accessible through memory
pointer registers (MP0 or MP1).
Indirect addressing register
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] ([02H]) will
access data memory pointed to by MP0 (MP1).
Reading location 00H (02H) itself indirectly
will return the result 00H. Writing indirectly
results in no operation.
The memory pointer registers (MP0 and MP1)
are 8-bit registers.
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RAM mapping