參數(shù)資料
型號: HT48C10-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 13/43頁
文件大?。?/td> 274K
代理商: HT48C10-1
HT48C10-1
13
January 4, 2001
The HALT mode stops the system oscillator
and ignores an external signal to conserve
power.
If an RC oscillator is used, an external resistor
between OSC1 and VDD is required and the
resistance must range from 51k
system clock, divided by 4, is available on
OSC2, which can be used to synchronize exter-
nal logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of oscillation may vary with VDD, tempera-
tures and the chip itself due to process varia-
tions. It is, therefore, not suitable for timing
sensitive operations where an accurate oscilla-
tor frequency is desired.
to 1M . The
If the Crystal oscillator is used, a crystal across
OSC1 and OSC2 is needed to provide the feed-
back and phase shift required for the oscillator,
and no other external components are required.
Instead of a crystal, a resonator can also be con-
nected between OSC1 and OSC2 to get a fre-
quency reference, but two external capacitors
in OSC1 and OSC2 are required. If the internal
RC oscillator is used, the OSC1 and OSC2 can
be selected as general I/O lines or an 32768Hz
crystal oscillator (RTC OSC). Also, the frequen-
cies of the internal RC oscillator can be
3.2MHz, 1.6MHz, 800kHz and 400kHz (de-
pended by options).
The WDT oscillator is a free running on-chip RC
oscillator, and no external components are re-
quired.Evenifthesystementersthepowerdown
mode, the system clock is stopped, but the WDT
oscillator still works with a period of approxi-
mately 78 s. The WDT oscillator can be disabled
by ROM code option to conserve power.
Watchdog Timer
WDT
The clock source of WDT is implemented by a
dedicated RC oscillator (WDT oscillator), RTC
clock or instruction clock (system clock divided
by4),decidedbyROMcodeoption.Thistimeris
designed to prevent a software malfunction or
sequence from jumping to an unknown location
with unpredictable results. The Watchdog
Timer can be disabled by a ROM code option. If
the Watchdog Timer is disabled, all the execu-
tions related to the WDT result in no operation.
The RTC clock is enabled only in the internal
RC+RTC mode.
Once the internal WDT oscillator (RC oscillator
withaperiodof65 s/5Vnormally)isselected,it
is first divided by 256 (8-stage) to get the nomi-
nal time-out period of approximately
16.6ms/5V. This time-out period may vary with
temperatures, VDD and process variations. By
invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2,
WS1,WS0(bit2,1,0oftheWDTS)cangivediffer-
ent time-out periods. If WS2, WS1, and WS0 are
allequalto1,thedivisionratioisupto1:128,and
the maximum time-out period is 2.2s/5V seconds.
If the WDT oscillator is disabled, the WDT clock
may still come from the instruction clock and op-
erate in the same manner except that in the
HALT state the WDT may stop counting and lose
its protecting purpose. In this situation the logic
can only be restarted by external logic. The high
nibble and bit 3 of the WDTS are reserved for
user'sdefinedflags,whichcanbeusedtoindicate
some specified status.
If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) or
32kHz crystal oscillator (RTC OSC) is strongly
recommended, since the HALT will stop the sys-
tem clock.
2 % / $ , ( * & =
; > 1 /* - . / $ #
"
# $ % & ' ( $ #
; > 1 /* - . / $ #
; / * ;
"
1 , $ ; * - /
"
* 3 $
0 / 1 * .
$ ( $ & /
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Watchdog Timer
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