HT48C10-1
12
January 4, 2001
Interrupts, occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
abled. In the case of simultaneous requests the
following table shows the priority that is ap-
plied. These can be masked by resetting the
EMI bit.
No. Interrupt Source Priority Vector
a
External Interrupt
1
04H
b
Timer/event
Counter Overflow
2
08H
The timer/event counter interrupt request flag
(TF), external interrupt request flag (EIF), en-
able timer/event counter bit (ETI), enable ex-
ternal interrupt bit (EEI) and enable master
interrupt bit (EMI) constitute an interrupt con-
trol register (INTC) which is located at 0BH in
the data memory. EMI, EEI, ETI are used to
control the enabling/disabling of interrupts.
These bits prevent the requested interrupt
from being serviced. Once the interrupt request
flags (TF, EIF) are set, they will remain in the
INTC register until the interrupts are serviced
or cleared by a software instruction.
It is recommended that a program does not
use the "CALL subroutine" within the inter-
rupt subroutine. Interrupts often occur in an
unpredictable manner or need to be serviced
immediately in some applications. If only one
stack is left and enabling the interrupt is not
well controlled,theoriginalcontrolsequencewill
be damaged once the "CALL" operates in the in-
terrupt subroutine.
Oscillator configuration
There are 3 oscillator circuits in the
microcontroller.
All of them are designed for system clocks,
namely the external RC oscillator, the external
Crystal oscillator and the internal RC
oscillator, which are determined by the ROM
code option. No matter what oscillator type is
selected, the signal provides the system clock.
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt
(1= enabled; 0= disabled)
1
EEI
Controls the external interrupt
(1= enabled; 0= disabled)
2
ETI
Controls the timer/event counter interrupt
(1= enabled; 0= disabled)
3
Unused bit, read as "0"
4
EIF
External interrupt request flag
(1= active; 0= inactive)
5
TF
Internal timer/event counter request flag
(1= active; 0= inactive)
6
Unused bit, read as "0"
7
Unused bit, read as "0"
INTC register
# 2 % / ' ( % & 1 ( ( ' / * #
6. & ( - 3 $ A 8
% & 1 ( ( ' / * #
0 $ . # ' 1 .
)
0 9
System oscillator