參數(shù)資料
型號: HT46R47
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit OTP Battery Charger Controller
中文描述: 8位檢察官電池充電器控制器
文件頁數(shù): 19/45頁
文件大?。?/td> 588K
代理商: HT46R47
HT46R47
Rev. 1.40
19
July 18, 2001
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0
Logical
Input
Logical
Output
Logical
Input
PWM
It is recommended that unused or not bonded
out I/O lines should be set as output pins by
software instruction to avoid consuming power
under input floating state.
PWM
The microcontroller provides 1 channel (6+2)
bits PWM output shared with PD0. The PWM
channel has its data register denoted as PWM
(1AH). The frequency source of the PWM coun-
ter comes from f
SYS
. The PWM register is an
eight bits register. The waveforms of PWM out-
put are as shown. Once the PD0 is selected as
the PWM output and the output function of
PD0 is enabled (PDC.0= 0 ), writing 1 to PD0
data register will enable the PWM output func-
tion and writing 0 will force the PD0 to stay
at 0 .
A PWM cycle is divided into four modulation cy-
cles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock
period. In a (6+2) bit PWM function, the con-
tents of the PWM register is divided into two
groups. Group 1 of the PWM register is denoted
by DC which is the value of PWM.7~PWM.2.
The group 2 is denoted by AC which is the value
of PWM.1~PWM.0.
In a PWM cycle, the duty cycle of each modula-
tion cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
Modulation cycle i
(i=0~3)
i<AC
DC
1
64
i AC
DC
64
The modulation frequency, cycle frequency and
cycle duty of the PWM output signal are sum-
marized in the following table.
PWM
Modulation
Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
f
SYS
/64
f
SYS
/256
[PWM]/256
A/D converter
The 4 channels and 9-bit resolution A/D (8-bit
accuracy) converter are implemented in this
microcontroller. The reference voltage is VDD.
The A/D converter contains 4 special registers
which are; ADRL (20H), ADRH (21H), ADCR
(22H) and ACSR (23H). The ADRH and ADRL
are A/D result register higher-order byte and
lower-order byte and are read-only. After the
A/D conversion is completed, the ADRH and
ADRL should be read to get the conversion re-
sult data. The ADCR is an A/D converter con-
trol register, which defines the A/D channel
number, analog channel select, start A/D con-
(
E
F G
E
F G
E
F G
E
F G
% 1 % ' # B
(
+ ) 2 , ' & . 0 ) - / # " 0 ) 2 B
PWM
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