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參數(shù)資料
| 型號(hào)： | HT46R47 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit OTP Battery Charger Controller |
| 中文描述： | 8位檢察官電池充電器控制器 |
| 文件頁數(shù)： | 13/45頁 |
| 文件大?。?/td> | 588K |
| 代理商： | HT46R47 |
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HT46R47
Rev. 1.40
13
July 18, 2001
Timer can be disabled by a ROM code option. If
the Watchdog Timer is disabled, all the execu-
tionsrelatedtotheWDTresultinnooperation.
Once the internal oscillator (RC oscillator with
a period of 72 s/5V normally) is selected, it is
first divided by 256 (8-stage) to get the nominal
time-out period of approximately 18.6ms/5V.
This time-out period may vary with tempera-
tures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can
be realized and the maximum time-out period
is 2.3s/5V~4.7s/5V seconds. If the WDT oscilla-
tor is disabled, the WDT clock may still come
from the instruction clock and operate in the
samemannerexceptthatintheHALTstatethe
WDT may stop counting and lose its protecting
purpose. In this situation the logic can only be
restarted by external logic.
If the device operates in a noisy environment, us-
ing the on-chip RC oscillator (WDT OSC) is
strongly recommended, since the HALT will stop
the system clock.
The WDT overflow under normal operation will
initialize
chip reset
and set the status bit
TO . But in the HALT mode, the overflow will
initialize a warm reset , and only the PC and
SP are reset to zero. To clear the contents of
WDT, three methods are adopted; external re-
set (a low level to RES), software instruction
and a "HALT" instruction. The software in-
struction include CLR WDT and the other set
CLR WDT1 and CLR WDT2 . Of these two
types of instruction, only one can be active de-
pending on the ROM code option
times selection option . If the CLR WDT is se-
lected (i.e. CLRWDT times equal one), any exe-
cution of the CLR WDT instruction will clear
the WDT. In the case that CLR WDT1 and
CLR WDT2 are chosen (i.e. CLRWDT times
equal two), these two instructions must be exe-
cuted to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
CLR WDT
Power down operation
HALT
The HALT mode is initialized by the HALT
instruction and results in the following...
The system oscillator will be turned off but
the WDT oscillator keeps running (if the
WDT oscillator is selected).
The contents of the on chip RAM and regis-
ters remain unchanged.
WDT will be cleared and recounted again (if
the WDT clock is from the WDT oscillator).
All of the I/O ports maintain their original sta-
tus.
The PD flag is set and the TO flag is cleared.
ThesystemcanleavetheHALTmodebymeans
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a warm re-
set . After the TO and PD flags are examined,
the reason for chip reset can be determined.
The PD flag is cleared by system power-up or
executing the CLR WDT instruction and is
set when executing the
The TO flag is set if the WDT time-out occurs,
and causes a wake-up that only resets the PC
and SP; the others keep their original status.
HALT
instruction.
The port A wake-up and interrupt methods can
be considered as a continuation of normal exe-
cution. Each bit in port A can be independently
selected to wake up the device by the ROM code
option. Awakening from an I/O port stimulus,
the program will resume execution of the next
instruction. If it is awakening from an inter-
rupt, two sequences may happen. If the related
interrupt is disabled or the interrupt is enabled
but the stack is full, the program will resume
execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the reg-
ular interrupt response takes place. If an
interrupt request flag is set to 1 before enter-
ing the HALT mode, the wake-up function of
the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 t
SYS
(sys-
tem clock period) to resume normal operation.
Inotherwords,adummyperiodwillbeinserted
after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual inter-
rupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the
nextinstructionexecution,thiswillbeexecuted
immediately after the dummy period is fin-
ished.
To minimize power consumption, all the I/O
pins should be carefully managed before enter-
ing the HALT status.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HT46R47(18DIP-A) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HT46R47(18SOP-A) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| HT46R47E | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective A/D Type 8-Bit MCU |
| HT46R47-H | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective A/D Type 8-Bit OTP MCU |
| HT46R48 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Cost-Effective A/D Type 8-Bit OTP MCU |
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