HT46R47
Rev. 1.40
18
July 18, 2001
on pull-high options). Each bit of these in-
put/outputlatchescanbesetorclearedby SET
[m].i and CLR [m].i (m=12H, 14H or 18H) in-
structions.
Some instructions first input data and then fol-
low the output operations. For example, SET
[m].i , CLR [m].i , CPL [m] , CPLA [m] read
the entire port states into the CPU, execute the
defined operations (bit-operation), and then
write the results back to the latches or the accu-
mulator.
Each line of port A has the capability of wak-
ing-up the device. The highest 4-bit of port B and
7 bits of port D are not physically implemented;
on reading them a 0 is returned whereas writ-
ing then results in a no-operation. See Applica-
tion note.
Each I/O line has a pull-high option. Once the
pull-high option is selected, the I/O line has a
pull-high resistor, otherwise, there s none.
Take note that a non-pull-high I/O line operat-
ing in input mode will cause a floating state.
The PA3 is pin-shared with the PFD signal. If
the PFD option is selected, the output signal in
output mode of PA3 will be the PFD signal gen-
erated by timer/event counter overflow signal.
The input mode always remaining its original
functions. Once the PFD option is selected, the
PFD output signal is controlled by PA3 data
register only. Writing 1 to PA3 data register
will enable the PFD output function and writ-
ing 0 will force the PA3 to remain at 0 . The
I/O functions of PA3 are shown below.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
PA3
Logical
Input
Logical
Output
Logical
Input
PFD
(Timer on)
Note:
The PFD frequency is the timer/event
counteroverflowfrequencydividedby2.
The PA5 and PA4 are pin-shared with INT and
TMR pins respectively.
The PB can also be used as A/D converter in-
puts. The A/D function will be described later.
There is a PWM function shared with PD0. If
the PWM function is enabled, the PWM signal
will appear on PD0 (if PD0 is operating in out-
put mode). The I/O functions of PD0 are as
shown.
9
:
5
( ) " ' 1
( ) "
- ' 1
1 $ . # +
& = # 7 , /
9 ) - ' 1 :
# & 2 & . & # * 0 $ . # "
9
) "
:
D
!
D
D
!
D
) - . " ) '0 .
& . &, $
" 0 . # ) - . " ) '# * 0 $ . # "
3 0 / # $ # .
# & 2 ) - . " ) '# * 0 $ . # "
" 0 . # & . & # * 0 $ . # "
& . &0 .
5
6
5
Input/output ports