參數(shù)資料
型號(hào): HT46R24
廠商: Holtek Semiconductor Inc.
英文描述: A/D Type 8-Bit MCU
中文描述: 的A / D型8位微控制器
文件頁數(shù): 6/49頁
文件大小: 393K
代理商: HT46R24
HT46R24/HT46C24
Rev. 1.50
6
May 3, 2004
Functional Description
Execution Flow
The system clock is derived from either a crystal or an
RC oscillator. It is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles. Instruction fetching and ex-
ecution are pipelined in such a way that a fetch takes
one instruction cycle while decoding and execution
takes the next instruction cycle. The pipelining scheme
makes it possible for each instruction to be effectively
executed in a cycle. If an instruction changes the value
of the program counter, two cycles are required to com-
plete the instruction.
Program Counter
PC
The program counter (PC) is 13 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
specify a maximum of 8192 addresses. After accessing
a program memory word to fetch an instruction code,
the value of the PC is incremented by 1. The PC then
points to the memory word containing the next instruc-
tion code. When executing a jump instruction, condi-
tional skip execution, loading a PCL register, a
subroutine call, an initial reset, an internal interrupt, an
external interrupt, or returning from a subroutine, the PC
manipulates the program transfer by loading the ad-
dress corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL per-
forms a short jump. The destination is within 256 loca-
tions.
When a control transfer takes place, an additional
dummy cycle is required.
0
-
0
-
0
-
+
# *
* 9
;
<
*
* 9
4 ;
+
# *
* 9
=
;
<
*
* 9
;
+
# *
* 9
=
;
<
*
* 9
=
;
=
=
*
.
>
* 9
*
. ;
Execution Flow
Mode
Program Counter
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
A/D Converter Interrupt
I
2
C Bus Interrupt
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Skip
PC+2
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*12~*0: Program counter bits
#12~#0: Instruction code bits
S12~S0: Stack register bits
@7~@0: PCL bits
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