參數(shù)資料
型號(hào)： HT46R24
廠商： Holtek Semiconductor Inc.
英文描述： A/D Type 8-Bit MCU
中文描述： 的A / D型8位微控制器
文件頁(yè)數(shù)： 26/49頁(yè)
文件大?。?/td> 393K
代理商： HT46R24
HT46R24/HT46C24
Rev. 1.50
26
May 3, 2004
Data Byte
The data is 8 bits and is sent after the slave device has
acknowledged the slave address. The first bit is MSB
and the 8th bit is LSB. The receiver sends the acknowl-
edge signal ( 0 ) and continues to receive the next one
byte data. If the transmitter checks and there s no ac-
knowledge signal, then it release the SDA line, and the
master sends a STOPsignal to release the I
2
C Bus. The
data is stored in the HDR register. The transmitter must
write data to the HDR before transmitting data and the
receiver must read data from the HDR after receiving
data.
Receive Acknowledge Bit
When the receiver wants to continue to receive the next
data byte, it generates an acknowledge bit (TXAK) at
the 9th clock. The transmitter checks the acknowledge
bit (RXAK) to continue to write data to the I
2
C Bus or
change to receive mode and dummy read the HDR reg-
ister to release the SDA line and the master sends the
STOP signal.
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Data Timing Diagram
Options
Thefollowingshowskindsofoptionsinthedevice.ALLtheoptionsmustbedefinedtoensurepropersystemfunction.
Options
OSC type selection.
This option is to decide if an RC or crystal oscillator is chosen as system clock.
WDT source selection.
There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT.
CLRWDT times selection.
This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear
the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then
WDT can be cleared.
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the
chip from a HALT by a falling edge. (Bit option)
Pull-high selection.
This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA and PB
are bit option; PC, PD and PF are port option.
PFD selection:
If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as
the PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 re-
spectively.
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
PD2: level output or PWM2 output
PD3: level output or PWM3 output
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 2
12
, 2
13
, 2
14
and 2
15
I
2
C Bus function: enable or disable
LVR selection.
LVR has enable or disable options
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