參數(shù)資料
型號(hào)： HT46R24
廠商： Holtek Semiconductor Inc.
英文描述： A/D Type 8-Bit MCU
中文描述： 的A / D型8位微控制器
文件頁(yè)數(shù)： 23/49頁(yè)
文件大小： 393K
代理商： HT46R24
HT46R24/HT46C24
Rev. 1.50
23
May 3, 2004
The I
2
C Bus status register contains 5 bits. The HCF bit
is reset to 0 when one data byte is being transferred. If
one data transfer is completed, this bit is set to 1 . The
HAAS bit is set 1 when the address is match, and the
I
2
C Bus interrupt request flag is set to 1 . If the interrupt
is enabled and the stack is not full, a subroutine call to
location 10H will occur. Writing data to the I
2
C Bus con-
trol register clears HAAS bit. If the address is not match,
this bit is reset to 0 . The HBB bit is set to respond the
I
2
C Bus is busy. It mean that a STARTsignal is detected.
This bit is reset to 0 when the I
2
C Bus is not busy. It
means that a STOPsignal is detected and the I
2
C Bus is
free. The SRW bit defines the read/write command bit, if
the calling address is match. When HAAS is set to 1 ,
the device check SRW bit to determine whether the de-
vice is working in transmit or receive mode. When SRW
bit is set 1 , it means that the master wants to read data
from I
2
C Bus, the slave device must write data to I
2
C
Bus, so the slave device is working in transmit mode.
When SRW is reset to 0 , it means that the master
wants to write data to I
2
C Bus, the slave device must
read data from the bus, so the slave device is working in
receive mode. The RXAK bit is reset 0 indicates an ac-
knowledges signal has been received. In the transmit
mode, the transmitter checks RXAK bit to know the re-
ceiver which wants to receive the next data byte, so the
transmitter continue to write data to the I
2
C Bus until the
RXAK bit is set to 1 and the transmitter releases the
SDA line, so that the master can send the STOP signal
to release the bus.
The HADR bit7-bit1 define the device slave address. At
the beginning of transfer, the master must select a de-
vice by sending the address of the slave device. The bit
0 is unused and is not defined. If the I
2
C Bus receives a
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is match, the HAAS status
bit is set and generate an I
2
C Bus interrupt. In the ISR,
the slave device must check the HAAS bit to know the
I
2
C Bus interrupt comes from the slave address that has
match or completed one 8-bit data transfer. The last bit
ofthe8-bitdataisread/writecommandbit,itrespondsin
SRW bit. The slave will check the SRW bit to know if the
master wants to transmit or receive data. The device
check SRW bit to know it is as a transmitter or receiver.
Bit7~Bit1
Bit0
Slave Address
Note:
means undefined
HADR Register
The HDR register is the I
2
C Bus input/output data regis-
ter. Before transmitting data, the HDR must write the
data which needs to be transmitted. Before receiving
data, the device must dummy read data from HDR.
Transmit or Receive data from I
2
C Bus must be via the
HDR register.
At the beginning of the transfer of the I
2
C Bus, the de-
vice must initial the bus, the following are the notes for
initialing the I
2
C Bus:
Note:
1: Write the I
2
C Bus address register (HADR) to define
its own slave address.
2: Set HEN bit of I
2
C Bus control register (HCR) bit 0 to
enable the I
2
C Bus.
Label
Function
HEN
7
Enable/disable I
2
C Bus function
(0= disable; 1= enable)
6~5 Unused bit, read as 0
HTX
4
Defines the transmit/receive mode
(0= receive mode; 1= transmit)
TXAK
3
Enable/disable transmit acknowledge
(0=acknowledge;1=don tacknowledge)
0~2 Unused bit, read as 0
HCR Register
3: Set EHI bit of the interrupt control register 1 (INTC1)
bit 0 to enable the I
2
C Bus interrupt.
Label
(HSR)
Bits
Function
HCF
7
HCF is cleared to 0 when one data
byte is being transferred, HCF is set to
1 indicating 8-bit data communication
has been finished.
HAAS
6
HAAS is set to 1 when the calling ad-
dress has matched, and I
2
C Bus inter-
rupt will occur and HCF is set.
HBB
5
HBB is set to 1 when I
2
C Bus is busy
and HBB is cleared to 0 means that
the I
2
C Bus is not busy.
4~3 Unused bit, read as 0
SRW
2
SRW is set to
wants to read data from the I
2
C Bus, so
the slave must transmit data to the mas-
ter. SRW is cleared to
master wants to write data to the I
2
C
Bus, so the slave must receive data from
the master.
1
when the master
0
when the
1
Unused bit, read as 0
RXAK
0
RXAK is cleared to 0 when the master
receives an 8-bit data and acknowledg-
ment at the 9th clock, RXAK is set to 1
means not acknowledged.
HSR Register
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