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參數(shù)資料
| 型號： | HT46R24 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | A/D Type 8-Bit MCU |
| 中文描述： | 的A / D型8位微控制器 |
| 文件頁數(shù)： | 12/49頁 |
| 文件大?。?/td> | 393K |
| 代理商： | HT46R24 |
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HT46R24/HT46C24
Rev. 1.50
12
May 3, 2004
ing on the option
CLR WDT times selection option . If
the CLR WDT is selected (i.e. CLRWDT times equal
one), any execution of the CLR WDT instruction will
clear the WDT. In case CLR WDT1 and CLR WDT2
are chosen (i.e. CLRWDT times equal two), these two
instructions must be executed to clear the WDT; other-
wise, the WDT may reset the chip because of time-out.
If the WDT time-out period is selected f
s
/2
12
(option), the
WDT time-out period ranges from f
s
/2
12
~f
s
/2
13
, since the
CLR WDT
or
CLR WDT1
instructions only clear the last two stages of the WDT.
and
CLR WDT2
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator turned off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
The contents of the on-chip RAM and registers remain
unchanged
The WDT will be cleared and start recounting (if the
WDT clock source is from the WDT oscillator or the
real time clock)
All of the I/O ports maintain their original status
The PDF flag is set and the TO flag is cleared
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port Aor a
WDT overflow. An external reset causes a device initial-
ization and the WDT overflow performs a warm reset .
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared
by system power-up or by executing the CLR WDT in-
struction and is set when executing the HALT instruc-
tion. On the other hand, the TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC program counter and SP; and leaves the others
in their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the option. Awakening from an I/O port stimu-
lus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may occur. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the pro-
gram will resume execution at the next instruction. But if
theinterruptisenabledandthestackisnotfull,theregu-
lar interrupt response takes place. When an interrupt re-
quest flag is set to 1 before entering the HALT mode,
the wake-up function of the related interrupt will be dis-
abled. If wake-up event occurs, it takes 1024 f
SYS
(sys-
tem clock period) to resume normal operation. In other
words, a dummy period is inserted after wake-up. If the
wake-up results from an interrupt acknowledgment, the
actual interrupt subroutine execution is delayed by more
than one cycle. However, if the wake-up results in the
next instruction execution, this will be executed per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which a reset may occur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a warm reset that
resets only the PC and SP, leaves the other circuits at
their original state. Some registers remain unaffected
during any other reset conditions. Most registers are re-
set to the initial condition when the reset conditions
are met. Examining the PDF and TO flags, the program
can distinguish between different chip resets .
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4
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6
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0
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7
)
*
.
6
-
0
Watchdog Timer
( ( >
( >
( D
+ E
( D (
+ E
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
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