參數(shù)資料
型號: HT46C64
廠商: Holtek Semiconductor Inc.
英文描述: A/D with LCD Type 8-Bit MCU
中文描述: 在A / D液晶型8位微控制器
文件頁數(shù): 9/47頁
文件大小: 345K
代理商: HT46C64
HT46R64/HT46C64
Rev. 1.40
9
September 21, 2004
These areas may function as a normal ROM depend-
ing upon the user s requirements.
Stack Register
STACK
The stack register is a special part of the memory used
to save the contents of the PC. The stack is organized
into 8 levels and is neither part of the data nor part of the
program, and is neither readable nor writeable. Its acti-
vated level is indexed by a stack pointer (SP) and is nei-
ther readable nor writeable. At the start of a subroutine
call or an interrupt acknowledgment, the contents of the
PC is pushed onto the stack. At the end of the subrou-
tine or interrupt routine, signaled by a return instruction
(RET or RETI), the contents of the PC is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a CALL is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent sixteen return addresses are stored).
Data Memory
RAM
The data memory (RAM) is designed with 224 8 bits,
and is divided into two functional groups, namely; spe-
cial function registers 32 8 bit and general purpose data
memory, 192 8 bit most of which are readable/writable,
although some are read only. The special function regis-
ter are overlapped in any banks.
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0; 0DH), a Timer/Event Counter 0 con-
trol register (TMR0C;0EH), a Timer/Event Counter 1
(TMR1H:0FH;TMR1L:10H), a Timer/Event Counter 1
control register (TMR1C; 11H), Interrupt control register
1 (INTC1;1EH), PWM data register (PWM0;1AH,
PWM1;1BH, PWM2;1CH, PWM3;1DH), the A/D result
lower-order byte register (ADRL;24H), the A/D result
higher-order byte register (ADRH;25H), the A/D control
register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The remaining space before the 40H is re-
served for future expanded usage and reading these lo-
cations will get
overlapping in each bank. The general purpose data
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands. All
of the data memory areas can handle arithmetic, logic,
increment, decrement and rotate operations directly.
Except for some dedicated bits, each bit in the data
00H . The space before 40H is
memory can be set and reset by SET [m].i and CLR
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RAM Mapping
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