參數(shù)資料
型號(hào)： HT46C64
廠商： Holtek Semiconductor Inc.
英文描述： A/D with LCD Type 8-Bit MCU
中文描述： 在A / D液晶型8位微控制器
文件頁(yè)數(shù)： 22/47頁(yè)
文件大小： 345K
代理商： HT46C64
HT46R64/HT46C64
Rev. 1.40
22
September 21, 2004
PWM
Modulation Frequency
PWM Cycle
Frequency
PWM Cycle
Duty
f
SYS
/64 for (6+2) bits mode
f
SYS
/128 for (7+1) bits mode
f
SYS
/256
[PWM]/256
A/D Converter
The 8 channels and 10 bits resolution A/D (9 bits accu-
racy) converter are implemented in this microcontroller.
The reference voltage is VDD. The A/D converter con-
tains 4 special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D con-
version is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D con-
version control bit and the end of A/D conversion flag. If
the users want to start an A/D conversion. Define PB
configuration, select the converted analog channel, and
give START bit a rising edge and falling edge (0
At the end of A/D conversion, the EOCB bit is cleared
and an A/D converter interrupt occurs. The ACSR is A/D
clock setting register, which is used to select the A/D
clock source.
1
0).
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is powered-on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure that the A/D conversion is completed,
the START should remain at
0
until the EOCB is
cleared to 0 (end of A/D conversion).
The bit 7 of the ACSR is used for testing purposes only.
It can not be used by the users.
The bit1 and bit0 of the ACSR are used to select A/D
clock sources.
Label
(ACSR)
Bits
Function
ADCS0
ADCS1
0
1
Selects the A/D converter clock
source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
2~6 Unused bit, read as 0
TEST
7
For test mode used only
ACSR Register
Label
(ADCR)
Bits
Function
ACS0
ACS1
ACS2
0
1
2
Defines the analog channel select.
PCR0
PCR1
PCR2
3
4
5
Defines the port B configuration se-
lect. If PCR0, PCR1 and PCR2 are all
zero, the ADC circuit is power off to re-
duce power consumption
EOCB
6
Provides response at the end of the
A/D conversion.
(0= end of A/D conversion)
START
7
Starts the A/D conversion. (0
start; 0
1= reset A/D converter)
1
0=
ADCR Register
ACS2
ACS1
ACS0
Analog Channel
0
0
0
A0
0
0
1
A1
0
1
0
A2
0
1
1
A3
1
0
0
A4
1
0
1
A5
1
1
0
A6
1
1
1
A7
Analog Input Channel Selection
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
A0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
A1
A0
0
1
1
PB7
PB6
PB5
PB4
PB3
A2
A1
A0
1
0
0
PB7
PB6
PB5
PB4
A3
A2
A1
A0
1
0
1
PB7
PB6
PB5
A4
A3
A2
A1
A0
1
1
0
PB7
PB6
A5
A4
A3
A2
A1
A0
1
1
1
A7
A6
A5
A4
A3
A2
A1
A0
Port B Configuration
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