HT46R64/HT46C64
Rev. 1.40
20
September 21, 2004
The I/O function of PA0/PA1 are shown below.
PA0 I/O
I
I
O O O O O O O O
PA1 I/O
I
O
I
I
I
O O O O O
PA0 Mode
X
X
C
B
B
C
B
B
B
B
PA1 Mode
X
C
X
X
X
C C C
B
B
PA0 Data
X
X
D
0
1 D
0
0
1
0
1
PA1 Data
X
D
X
X
X D1 D D
X
X
PA0 Pad Status
I
I
D
0
B D
0
0
B
0
B
PA1 Pad Status
I
D
I
I
I
D
1
D D
0
B
Note:
I input; O output
D, D0, D1 Data
B buzzer option, BZ or BZ
X don t care
C CMOS output
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2/PD3. If the PWM
function is enabled, the PWM0/PWM1/PWM2/PWM3
signal will appear on PD0/PD1/PD2/PD3 (if
PD0/PD1/PD2/PD3 is operating in output mode). Writ-
ing 1 to PD0~PD3 data register will enable the PWM
outputfunctionandwriting 0 willforcethePD0~PD3to
remain at 0 . The I/O functions of PD0/PD1/PD2/PD3
are as shown.
I/O
Mode
I/P
(Normal)
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
PD0
PD1
PD2
PD3
Logical
Input
Logical
Output
Logical
Input
PWM0
PWM1
PWM2
PWM3
It is recommended that unused or not bonded out I/O
linesshouldbesetasoutputpinsbysoftwareinstruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
Timer
Timer
Preload
Value
PA3 Data
Register
PA3 Pad
State
PFD
Frequency
OFF
X
0
0
X
OFF
X
1
U
X
ON
N
0
0
X
ON
N
1
PFD
f
TMR
/[2 (M-N)]
Note:
X stands for unused
U stands for unknown
M is 256 for PFD0 or 65536 for PFD1
N is preload value for timer/event counter
f
TMR
is input clock frequency for timer/event
counter
PWM
The microcontroller provides 4 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1/PD2/PD3.ThePWMchannelshavetheirdata
registers denoted as PWM0 (1AH), PWM1 (1BH),
PWM2 (1CH) and PWM3 (1DH). The frequency source
of the PWM counter comes from f
SYS
. The PWM regis-
ters are four 8-bit registers. The waveforms of PWM out-
puts are as shown. Once the PD0/PD1/PD2/PD3 are
selected as the PWM outputs and the output function of
PD0/PD1/PD2/PD3 are enabled (PDC.0/PDC.1/
PDC.2/PDC.3= 0 ), writing 1 to PD0/PD1/PD2/PD3
!
!
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Input/Output Ports