參數(shù)資料
型號(hào): HT46C64
廠商: Holtek Semiconductor Inc.
英文描述: A/D with LCD Type 8-Bit MCU
中文描述: 在A / D液晶型8位微控制器
文件頁數(shù): 14/47頁
文件大小: 345K
代理商: HT46C64
HT46R64/HT46C64
Rev. 1.40
14
September 21, 2004
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from 2
12
/f
S
to 2
15
/f
S
selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 14H occurs.
Real Time Clock
RTC
The real time clock (RTC) is operated in the same man-
ner as the time base that is used to supply a regular in-
ternal interrupt. Its time-out period ranges from f
S
/2
8
to
f
S
/2
15
by software programming . Writing data to RT2,
RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a sub-
routine call to location 18H occurs.
RT2
RT1
RT0
RTC Clock Divided Factor
0
0
0
2
8
*
0
0
1
2
9
*
0
1
0
2
10
*
0
1
1
2
11
*
1
0
0
2
12
1
0
1
2
13
1
1
0
2
14
1
1
1
2
15
Note: * not recommended to be used
Power Down Operation
HALT
The HALT mode is initialized by the HALT
and results in the following.
instruction
The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
The contents of the on-chip RAM and of the registers
remain unchanged.
The WDT is cleared and start recounting (if the WDT
clocksourceisfromtheWDToscillatorortherealtime
clock oscillator).
All I/O ports maintain their original status.
The PDF flag is set but the TO flag is cleared.
LCD driver is still running (if the WDT OSC or RTC
OSC is selected).
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initial-
ization, and the WDT overflow performs a warm reset .
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared by
system power-up or by executing the CLR WDT in-
struction, and is set by executing the HALT instruction.
On the other hand, the TO flag is set if WDT time-out oc-
curs, and causes a wake-up that only resets the PC (Pro-
gram Counter) and SP, and leaves the others at their
original state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terruptisenabled,andthestackisnotfull,theregularin-
terrupt response takes place.
7
( ( ( ( ( ( ( (
&
4 (
(
= D
6
+
(
4
- & ,
/
- &
Real Time Clock
( ( ( ( ( ( ( (
&
7
6
$
(
7
( ; & -
, & -
4
<
*
9 9
( ; & -
, & -
:
<
( *
(
- & ,
/
- &
Time Base
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