HT46R64/HT46C64
Rev. 1.40
15
September 21, 2004
When an interrupt request flag is set before entering the
HALT status, the system cannot be awakened using
that interrupt.
If wake-up events occur, it takes 1024 t
SYS
(system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which reset may occur.
RES is reset during normal operation
RES is reset during HALT
WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a warm reset that
resets only the PC and SP and leaves the other circuits
at their original state. Some registers remain unaffected
during any other reset conditions. Most registers are re-
set to the initial condition once the reset conditions are
met. Examining the PDF and TO flags, the program can
distinguish between different chip resets .
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT Wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
PC
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT,RTC,TimeBase
Cleared. After master reset,
WDT starts counting
Timer/event Counter
Off
Input/output Ports
Input mode
SP
Pointstothetopofthestack
+ +
+
+ D
3 E
+ D +
3 E
Reset Circuit
Note:
* Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
(
5
%
( (
Reset Timing Chart
'
8 " $
'
5
=
6
6
A
5
(
+ 5 @
(
6
'
(
Reset Configuration