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參數(shù)資料
| 型號(hào)： | HSP50215 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital UpConverter(數(shù)字上變頻器) |
| 中文描述： | 數(shù)字上變頻器（數(shù)字上變頻器） |
| 文件頁(yè)數(shù)： | 20/21頁(yè) |
| 文件大?。?/td> | 162K |
| 代理商： | HSP50215 |
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3-20
AC Electrical Specifications
V
CC
= 5
±
5%, T
A
= 0
o
C to 70
o
C, Commercial; T
A
= -40
o
C to 85
o
C, Industrial (Note 5)
PARAMETER
SYMBOL
52MHz
UNITS
MIN
MAX
REFCLK Clock Period (Commercial)
t
CP
19
-
ns
REFCLK Clock Period (Industrial)
t
CP
21
-
ns
REFCLK High
t
CH
7
-
ns
REFCLK Low
t
CL
7
-
ns
Setup Time CAS(15:0), SYNCIN to REFCLK
t
DS
6
-
ns
Hold Time CAS(15:0), SYNCIN to REFCLK
t
DH
1
-
ns
Setup Time A(9:0) to Rising Edges of WR or CE Low
t
AS
12
-
ns
Setup Time C(15:0) to Rising Edges of WR or CE Low
t
CS
6
-
ns
Hold Time A(9:0) to Rising Edges of WR or CE Low
t
AH
2
-
ns
Hold Time C(15:0) to Rising Edges of WR or CE Low
t
CH
2
-
ns
Read Address Low to Data Valid
t
ADO
-
16
ns
Rising Edge of WR or CE to FIFORDY High (FIFO Write)
t
WF
12
-
ns
REFCLK to OUT(15:0)
t
DO
-
8
ns
REFCLK to SYNCOUT, SAMPCLK and FIFORDY Valid
t
DOC
-
12
ns
WR High
t
WRH
7
-
ns
WR Low
t
WRL
7
-
ns
RD Low
t
RL
9
-
ns
RD LOW and CE LOW to Data Valid
t
RDO
-
8
ns
RD HIGH and CE HIGH to Output Disable
t
ROD
-
10
(Note 6)
ns
Output Enable Time
t
OE
-
7
ns
Output Disable Time
t
OD
-
8
(Note 6)
ns
Output Rise, Fall Time
t
RF
-
5
(Note 6)
ns
NOTES:
5. AC tests performed with C
L
= 40pF, I
OL
= 2mA, and I
OH
= -400
μ
A. Input reference level for CLK is 2.0V, all other inputs 1.5V.
Test V
IH
= 3.0V, V
IHC
= 4.0V, V
IL
= 0V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
AC Test Load Circuit
EQUIVALENT CIRCUIT
C
L
I
OH
1.5V
I
OL
DUT
SWITCH S
1
OPEN FOR I
CCSB
AND I
CCOP
S
1
±
TEST HEAD CAPACITANCE
HSP50215
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