- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385396 > HSP50110 (Intersil Corporation) Digital Quadrature Tuner(數(shù)字調(diào)諧器) PDF資料下載
參數(shù)資料
| 型號： | HSP50110 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| 中文描述： | 數(shù)字正交調(diào)諧器（數(shù)字調(diào)諧器） |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 207K |
| 代理商： | HSP50110 |
3-2
Pinout
HSP50110 (PLCC)
TOP VIEW
Pin Description
NAME
TYPE
DESCRIPTION
V
CC
-
+5V Power Supply.
GND
-
Ground.
IIN9-0
I
In-Phase Input. Data input for in-phase (real) samples. Format may be either two’s complement or offset binary format
(see I/O Formatting/Control Register in Table 9). IIN9 is the MSB.
QIN9-0
I
Quadrature Input. Data input for quadrature (imaginary) samples. Format may be either two’s complement or offset bi-
nary format (see I/O Formatting/Control Register in Table 9). QIN9 is the MSB.
ENI
I
Input Enable. When ENI is active ‘low’, data on IIN9-0 and QIN9-0 is clocked into the processing pipeline by the rising
edge of CLK. This input also controls the internal data processing as described in the Input Controller Section of the
data sheet. ENI is active ‘low’.
PH1-0
I
Carrier Phase Offset. The phase of the internally generated carrier frequency may be shifted by 0, 90, 180, or 270 de-
grees by controlling these pins (see Synthesizer/Mixer Section). The phase mapping for these inputs is given in Table 1.
CFLD
I
Carrier Frequency Load. This input loads the Carrier Frequency Register in the Synthesizer NCO (see
Synthesizer/Mixer Section). When this input is sampled ‘high’ by clock, the contents of the Microprocessor Interface
Holding Registers are transferred to the carrier frequency register in the Synthesizer NCO (see Microprocessor Inter-
face Section).
NOTE: This pin must be ‘low’ when loading other configuration data via the Microprocessor In-
terface. Active high Input.
COF
I
Carrier Offset Frequency Input. This serial input is used to load the Carrier Offset Frequency into the Synthesizer NCO
(see Serial Interface Section). The new offset frequency is shifted in MSB first by CLK starting with the clock cycle after
the assertion of COFSYNC.
COFSYNC
I
Carrier Offset Frequency Sync. This signal is asserted one CLK cycle before the MSB of the offset frequency data word
(see Serial Interface Section).
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I
I
I
G
I
I
I
O
L
S
S
S
S
V
C
S
S
H
I
I
I
I
G
S
S
C
C
C
C
V
C
C
C
C
C
C
C
A
A
G
A
R
W
C
IIN5
IIN4
IIN3
IIN2
GND
IIN1
IIN0
ENI
QIN9
QIN8
QIN7
QIN6
QIN5
QIN4
V
CC
QIN3
QIN2
QIN1
QIN0
PH1
PH0
IOUT1
IOUT0
DATARDY
V
CC
CLK
GND
QOUT9
QOUT8
QOUT7
QOUT6
QOUT5
GND
QOUT4
QOUT3
IOUT3
IOUT2
QOUT2
QOUT1
QOUT0
OEQ
V
CC
HSP50110
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| HSP50214VC | Programmable Downconverter |
| HSP50214VI | Programmable Downconverter |
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Quadrature Tuner |
| HSP50110JC-52 | 功能描述:調(diào)諧器 DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,COMM RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| HSP50110JC-52Z | 功能描述:調(diào)諧器 W/ANNEAL DIGTL TUNER 84 PLCC 52MHZ RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| HSP50110JC-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Tuner Circuit |
| HSP50110JI-52 | 功能描述:調(diào)諧器 DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDUSTRIAL RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。