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參數(shù)資料
| 型號(hào)： | HSP50110 |
| 廠商： | Intersil Corporation |
| 英文描述： | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| 中文描述： | 數(shù)字正交調(diào)諧器（數(shù)字調(diào)諧器） |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 207K |
| 代理商： | HSP50110 |
3-18
TABLE 6. CENTER FREQUENCY REGISTER
DESTINATION ADDRESS = 0
BIT
POSITIONS
FUNCTION
DESCRIPTION
31-0
Center Frequency
This register controls the center frequency of the Synthesizer/Mixer NCO. This 32-bit two’s complement
value sets the center frequency as described in the Synthesizer/Mixer Section. Center
F
C
F
S
H
Format: [XXXXXXXX]H
Range: (0000000 - FFFFFFF)H.
TABLE 7. INPUT THRESHOLD REGISTER
DESTINATION ADDRESS = 2
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
Input Level Detector
Threshold
This register sets the magnitude threshold for the Input Level Detector (see Input Level Detector Section).
This 8-bit value is a fractional unsigned number whose format is given by:
2
0
. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
The possible threshold values range from 0 to 1.9961 (00 - FF)
H
. The magnitude range for complex inputs
is 0.0 - 1.4142 while that for real inputs is 0.0 - 1.0. Threshold values of greater than 1.4142 will never be
exceeded.
31-8
Reserved.
TABLE 8. AGC CONTROL REGISTER
DESTINATION ADDRESS = 3
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
AGC Level Detector
Threshold
Magnitude threshold for the AGC Level Detector (see AGC Section). The magnitude threshold is repre-
sented as an 8-bit fractional unsigned value with the following format:
2
0
. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
The possible threshold values range from 0 to 1.9961. However, the usable range of threshold values
span from 0 to 1.4142, since full scale outputs on both I and Q correspond to a magnitude of
. Thresholdvaluesofgreaterthan1.4142willforcetheAGCgaintotheupperlimit.
15-8
Loop Filter Upper Limit
(Maximum Gain)
Upper limit for Loop Filter’s accumulator (see AGC Section). The three most significant bits are the expo-
nent and the five least significant bits represent the mantissa (see Figure 3). The three exponent bits map
to bit positions 15-13 (15 is the MSB) and the five mantissa bits map to bit positions 12-8 (12 is the MSB).
(EEE.MMMMM)
2.
Lower limit for Loop Filter’s accumulator (see AGC Section). The format is the same as that for the upper
limit described above. The 3 exponent bits map to bit positions 23-21 (23 is the MSB) and the mantissa
bits map to bit positions 20-16 (20 is the MSB). (EEE.MMMMM)
2.
Programmable part of Loop Gain word (see AGC Section). The Loop Gain value increments or decre-
ments the Loop Filter’s Accumulator at bit positions 2
-6
through 2
-13
as shown in Figure 3. The 8-bit loop
gain is loaded into bit positions 31-24 (31 is the MSB and maps to the 2
-6
position in the Accumulator).
(GGGGGGGG)
2.
23-16
Loop Filter Lower Limit
(Minimum Gain)
31-24
Programmable Loop
Gain
TABLE 9. I/O FORMATTING/CONTROL
DESTINATION ADDRESS = 4
BIT
POSITION
FUNCTION
DESCRIPTION
0
Input Format
0 = Two’s complement input format, 1 = Offset binary input format.
Note: if a real input with offset binary weighting is used, the unused quadrature input pins should be tied
to 1000000000.
1
Input Mode
0 = Input Controller operates in Interpolated Input Mode.
1 = Input Controller operates in Gated Input Mode.
(See Input Controller Section).
Center Frequency
CF
H
-------
2
32
COF
H
–
=
=
I
2
Q
2
+
2
1.4142
=
=
HSP50110
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50110_01 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Quadrature Tuner |
| HSP50110JC-52 | 功能描述:調(diào)諧器 DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,COMM RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| HSP50110JC-52Z | 功能描述:調(diào)諧器 W/ANNEAL DIGTL TUNER 84 PLCC 52MHZ RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
| HSP50110JC-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Tuner Circuit |
| HSP50110JI-52 | 功能描述:調(diào)諧器 DIGITAL QUADRATURE TUNER 84 PLCC,52MHZ,INDUSTRIAL RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
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