參數(shù)資料
型號: HSC-INTERFACEBOARD
廠商: Analog Devices, Inc.
英文描述: 1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
中文描述: 1.75 MSPS的,4 10-Bit/12-Bit并行模數(shù)轉(zhuǎn)換器毫瓦
文件頁數(shù): 4/16頁
文件大小: 197K
代理商: HSC-INTERFACEBOARD
REV. A
AD7470/AD7472
TIMING SPECIFICATIONS
1
(V
DD
= +2.7 V to +5.25 V, REF IN = 2.5 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
–4–
AD7470
Limit at T
MIN
, T
MAX
Parameter
f
CLK 2
AD7472
Units
Description
10
30
436.42
1
10
10
30
0
0
20
15
8
0
135
100
10
26
531.66
1
10
10
30
0
0
20
15
8
0
135
100
kHz min
MHz max
ns min
μ
s max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
t
CONVERT
t
WAKEUP
t
1
t
23
t
CLK
= 1/f
CLK IN
Wake-Up Time
CONVST
Pulsewidth
CONVST
to BUSY Delay, V
DD
= 5 V
CONVST
to BUSY Delay, V
DD
= 3 V
BUSY to
CS
Setup Time
CS
to
RD
Setup Time
RD
Pulsewidth
Data Access Time After Falling Edge of
RD
Bus Relinquish Time After Rising Edge of
RD
CS
to
RD
Hold Time
Acquisition Time
Quiet Time
t
3
t
44
t
5
t
64
t
75
t
8
t
9
t
10
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V. See
Figure 1.
2
Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of
CONVST
.
3
t
2
is 35 ns max @ +125
°
C.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200 A
I
OL
200 A
I
OH
C
L
50pF
TO OUTPUT
PIN
+1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
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