參數(shù)資料
型號： HMS97C7134
英文描述： [Monitor]
中文描述： [顯示器]
文件頁數(shù)： 64/86頁
文件大?。?/td> 1508K
代理商： HMS97C7134
HMS91C7134
64
November.2001 ver1.0
Both the HCHG and the VCHG signals are combined and con-
nected to the internal interrupt. Interrupt will be issued when
change is continuously detected like following table.
Due to this fast interrupt the S-correction can be set to a safe level
before any damage to the deflection circuitry will occur.
Table 19-3 Time interval between mode change and interrupt
Internally there are two 12-bit counter for HSYNC and VSYNC
period check , HSYNC counter count up from 0 to 4096 for 4
HSYNC lines according to 12MHz clock, and VSYNC counter
count up from 0 to 4096 for one VSYNC line according to
125KHz clock. For HSYNC static state that HSYNC frequency
is under 12KHz, counter value is more than 4080 value,and for
VSYNC static state that VSYNC frequency is under 32Hz,
counter value is more than 4080 value.
HSYNC
HPnew < HPpre
HPnew x 61 to (4 x HPnew x 15) - (n x HPpre)
HPnew > HPpre
(4 x HPnew) x 3 - (n x HPpre)
POS => NEG
60 HSYNC lines
NEG => POS
60 HSYNC lines
VSYNC
Period
Period
Polarity
Polarity
VPnew < VPpre
(VPnew x 2 + VPprev) to (Vnew x 3)
VPnew > VPpre
(VPnew) to (VPnew x 2)
POS => NEG
3 VSYNC lines
NEG => POS
2 VSYNC lines
Mode change
Interval between mode change and interrupt
To Static State
(4 x HPnew) x 3 - (n x HPpre)
To Static State
(VPnew) to (VPnew x 2)
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