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| 型號： | HMS97C7134 |
| 英文描述： | [Monitor] |
| 中文描述： | [顯示器] |
| 文件頁數(shù)： | 24/86頁 |
| 文件大?。?/td> | 1508K |
| 代理商： | HMS97C7134 |
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HMS91C7134
24
November.2001 ver1.0
9. INTERRUPTS
There are interrupt requests from 9 sources as follows.
INT0 external interrupt
INT1 external interrupt
Timer0 interrupt
Timer1 interrupt
Timer2 interrupt
DDC interrupt
MD interrupt
VSYNC interrupt
I2C interrupt
9.1 Interrupt sources
INT0 external interrupt:
The INT0 can be either level-active or transition-active depend-
ing on bit IT0 in register TCON. The flag that actually generates
this interrupt is bit IE0 in TCON.
When an external interrupt is generated, the corresponding re-
quest flag is cleared by the hardware when the service routine is
vectored to only if the interrupt was transition-activated.
I
f the interrupt was level-activated then the interrupt request flag
remains set until the requested interrupt is actually generated.
Then it has to deactivate the request before the interrupt service
routine is completed, or else another interrupt will be generated.
INT1 external interrupt:
T
he INT1 can be either level-active or transition-active depend-
ing on bit IT1 in register TCON. The flag that actually generates
this interrupt is bit IE1 in TCON.
When an external interrupt is generated, the corresponding re-
quest flag is cleared by the hardware when the service routine is
vectored to only if the interrupt was transition-activated.
If the interrupt was level-activated then the interrupt request flag
remains set until the requested interrupt is actually generated.
Then it has to deactivate the request before the interrupt service
routine is completed, or else another interrupt will be generated.
MD interrupt:
A MD interrupt is generated by the hardware mode detector in
case of mode change, horizontal or vertical.
This flag has to be cleared by the software.
VSYNC interrupt:
The changing of the VSYNC level can generate an interrupt.
This depends on the setting that is programmed in the MDCON-
SFR. Via this register it is possible to enable the edge of the
VSYNC-signal that should generate the interrupt. Both edges can
be controlled separately.
The interrupt flag has to be cleared by the software.
DDC interrupt:
The DDC interrupt is generated either by bit INTR in the S1STA
register for DDC2B/DDC2AB/DDC2B+ protocol or by bit
DDC_int in the DDCCON register for DDC1 protocol or by bit
SWHINT bit in the DDCCON register when DDC protocol is
changed from DDC1 to DDC2.
Flags except the INTR have to be cleared by the software. INTR
flag is cleared by hardware.
I2C interrupt:
The interrupt of the second I2C is generated by bit INTR in the
register S2STA.
This flag is cleared by hardware.
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相關(guān)代理商/技術(shù)參數(shù) |
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