參數(shù)資料
型號(hào)： HMS97C7134
英文描述： [Monitor]
中文描述： [顯示器]
文件頁(yè)數(shù)： 53/86頁(yè)
文件大?。?/td> 1508K
代理商： HMS97C7134
HMS91C7134
November.2001 ver1.0
53
Serial Status Register(SXSTA)
SxSTA is a read-only register. The contents of this register may be used as a vector to a service routine. This optimized the response
time of the software and consequently that of the I2C-bus. The status codes for all possible modes of the I2C-bus interface are given
Table
Table 17-4 Serial status register
(SXSTA; S1STA:0D9H, S2STA:0DDH)
Table 17-5 Description of SxSTA
Data Shift Register(SXDAT; S1DAT, S2DAT)
SxDAT contains the serial data to be transmitted or data which has just been received. The MSB (bit7) is transmitted or
received first; I,e. data shifted from right to left.
Table 17-6 Serial data shift register
Addressing Register(SXADR)
This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as a slave receive/
transmitter.
Table 17-7 Address register(SLA6 to SLA0 : Own slave address.)
7
6
5
4
3
2
1
0
GC
STOP
INTR
TX_MODE
BBUSY
BLOST
/ACK_REP
SLV
BIT
7
SYMBOL
GC
FUNCTION
General Call flag.
6
STOP
STOP flag.
This bit is set when a STOP condition was received.
5
INTR
Bus busy state flag.
This bit is set when the bus is being used by another master. Otherwise, this bit is reset.
Interrupt flag.
This bit is set when a SIO interrupt is requested.
4
TX_MODE
Transmission mode flag.
This bit is set when the SIO is a transmitter. Otherwise, this bit is reset.
Bus lost flag.
This bit is set when the master loses the bus contention. Otherwise, this bit is reset.
1
/ACK_REP
Acknowledge response flag.
This bit is set when the receiver transmits the not acknowledge signal.
This bit is reset when the receiver transmits the acknowledge signal.
Slave mode flag.
This bit is set when the SIO plays role in the slave mode. Otherwise, this bit is reset.
BLOST
2
SLV
0
BBUSY
3
7
6
5
4
3
2
1
0
SxDAT7
SxDAT6
SxDAT5
SxDAT4
SxDAT3
SxDAT2
SxDAT1
SxDAT0
7
6
5
4
3
2
1
0
-
SLA6
SLA5
SLA4
SLA3
SLA2
SLA1
SLA0
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