
4-7
Power Dissipation The Easy Way
Fortunately there is a much easier method available for mea-
suring power dissipation and none of the above equations
ever need to be evaluated. Very simple lab equipment can
be used to obtain the measurements and simple calculations
can be used to obtain accurate results.
The simple method for evaluating power dissipation breaks
down the total power dissipation problem into high voltage
power dissipation and low voltage power dissipation.
Low Voltage Power Dissipation
The low voltage power dissipation includes low voltage leak-
age and switching losses associated with gating both of the
power switches. It also includes the CMOS switching losses
associated with both driver stages. As shown in Figure 8, the
upper and lower bias supplies are tied together and supplied
by bias voltage V
CC
, while capacitors C
L
are tied to both of
the HIP2500 outputs. Both inputs are then pulsed at the fre-
quency of interest and the average current, I
CC
is measured.
The total low voltage power dissipation is then simply the
product of I
CC
and V
CC
as shown in Equation 6 below:
PLV
Plotting the results of Equation 6 as a function of switching
frequency and the load capacitance of each of the power
switches yields a family of curves for the low voltage power
dissipation of the HIP2500 as shown in Figure 9.
If the quiescent bias current and CMOS switching losses are
subtracted from the above power calculation, what is left is
the power required to drive the gate-source capacitance of
the power switches. The power required from V
CC
to drive
the gates can also be calculated by Equation 7, where C
G
is
the combined equivalent gate capacitance of both power
switches. Half of this power is dissipated in the combined
source resistance of the driver and any external resistance
in the source circuit and the other half of the power is dissi-
pated in the sinking circuit, including any external resistance
in the sinking path.
CGfPWM
High Voltage Power Dissipation
The high voltage power dissipation component includes the
losses associated with the level-shifter and the tub charge
transfer power losses. This component is not affected by the
size of the power device being switched. Figure 9 shows the
test circuit which is used to measure the high voltage
level-shifter and high voltage leakage power losses.
By measuring I
S
and V
BUS
and calculating the product of
these measurements, one can obtain the value for total high
voltage power loss for the HIP2500. The value derived will
include both reverse leakage power due to the isolation tub
and two level-shift events. Both the turnon level-shift and the
turnoff level-shift events are included. The high voltage
power dissipation will increase directly with both switching
frequency and bus voltage level as shown in Figure 11.
Layout Issues
While a lot of effort was spent in designing the HIP2500 to
be immune to noise, poor layout can cause problems.
Particular attention should be paid to keeping the distance
between the HIP2500 and the power switches as short as
possible. If your design is experiencing any of these effects,
it may be helpful to first look at the possible causes in the
table: Layout Problems and Effects.
V
S
V
CC
C
L
C
L
I
CC
HO
LO
HIN
LIN
V
DD
V
B
V
CC
±
FIGURE 8. LOW VOLTAGE POWER DISSIPATION TEST
CIRCUIT
(EQ. 6)
VCCICC
=
P
SWITCHING FREQUENCY (kHz)
10
100
1000
0.01
0.1
1
10
V
S
= V
SS
= COM, V
BS
= V
CC
= 15V DC, T
A
= 25
o
C
ALL SWITCHING LOSSES ASSUMED TO BE IN IC
100pF
2100pF
907pF
FIGURE 9. LOW VOLTAGE POWER DISSIPATION vs
FREQUENCY
(EQ. 7)
PG
V2
=
V
BS
= 15V
C
L
C
L
HO
LO
HIN
LIN
V
BUS
(0 to 500V)
I
S
V
S
V
B
±
±
FIGURE 10. HIGH VOLTAGE POWER DISSIPATION TEST
CIRCUIT
Application Note 9010